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LOSTCIRCUITS	SHORTCUTS: A matter of 8 cores Dual Independent Buses FBDIMMs or back to the MTH FBDIMMs, Take 2 The S5000XVN Test Configuration Memory Bandwidth Latencies Intercore and cache communication DVD Shrink, & Mainconcept H.264 Futuremarks Cinebench, POV Ray TrueSpace and Render Power Power Consumption Final Thoughts Give Us Some Feedback on this Review
Intel's V8-Demo System "Octopussy"
(Review by MS, May 31, 2007)

Memory Subsystem: Latencies

Access latencies were horrendous in the Camino chipset with the memory controller hub, and placing the controller on the DIMM's PCB instead of having it on the motherboard can hardly be anticipated to be fundamentally different in that respect. We mentioned eralier that programs like Cachemem don't work in the Vista64 environment and ScienceMark is not generating representative latency measurements anyway, therefore, we resort to SiSoft Sandra again. Sandra also has, in addition to the "linear access", that is hitting memory addresses in a linear stride pattern, the option of generating random accesses, which essentially represents a page-miss scenario.

Linear Access

Access latencies [ns], lower is better

Random Access

Access latencies [ns], lower is better

Instead of running an entire gamut of data, we use Sandra's internal data base as reference. Note that the scale in both graphs is logarithmic. In the linear access graph, Intel's Core2 Duo E6700 comes in at roughly 30 ns (green trace) whereas the FBDIMM system takes almost 85 ns between linear accesses. However, it is not only the FBDIMM architecture that can increase latencies, another case in point is the ccNUMA architecture that is used for example on the QuadFX systems. Compared to those data that we measured at 134.4 ns (random) and 38.3 ns (linear), the Xeon system looks still rather good.

(BX80557E6300)

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