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LOSTCIRCUITS

SHORTCUTS:
Core 2 Duo: The light at the end of the tunnel
Core 2 Key Features
Specs and Numbers/ Testconfigurations
Benchmark Overview
Memory Performance 1
Memory Latencies
Power Plays
TrueSpace5.1 and Rendering Power
3dsmax 8.0
Cinebench 2003
3DMark'05
FarCry, F.E.A.R.
Call of Duty, DOOM3, Prey
Final Thoughts

Give Us Some Feedback on this Review

 Intel Core 2 Duo
Blinded by the light
(Review by MS, July 25, 2006)

The Shared Cache

From an architectural standpoint, the major factor holding back Intel’s performance was the data interface in the broadest sense. The processor side bus interfacing the CPU with the core logic appears very ineffective for anything but streaming applications, and particularly in an SMP situation (including dual core CPUs), the broad issue of the cache coherency is essentially a death-blow to any reasonable approach to further speeding up the processor. Briefly, because the caches were not shared, every piece of data, in order to be flipped back and forth between the cores had to be moved out to the main memory and from there, it had to be re-imported through the same bi-directional interface to the other half of the CPU. This takes a lot of time.

The solution is a complete change of the caching strategy, meaning that the cache of both CPUs is shared between them. Especially in the case of a bi-directional outside connection where data can only go one way at any given point in time, the cache sharing translates into a huge performance increase – at least on paper.

Shared vs. Independent L2 Cache

Having fast access to data is one thing but there is also the issue of executing the instructions better and faster. This is where the second improvement in the Core2 architecture takes place: the Intel Wide Dynamic Execution allows simultaneous execution of up to four full instructions simultaneously per core.

Intel Wide Dynamic Execution

Intel Core Duo T2600
(dual core)

next page: => Numbers and Test Configuration =>

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