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| Intel Core 2 Duo Blinded by the light | |
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(Review by MS, July 25, 2006) |
Memory Performance
Over the past few years, Intel has been pushing memory bandwidth over latency. However, other than by the memory itself, memory bandwidth is also limited by the CPU-to-system interface, in this case, the processor side bus (PSB) using the Advanced Gunning Transceiver Logic (AGTL). Starting with the Granite Bay chipset a few years ago, we saw the PSB bus frequency increase from 400 MHz data rate to 533 and 800 MHz and the latest iteration of the 975 chipset is running at no less than 1066 MHz data rate. In theory, 1066 MHz data rate allows the transfer of no less than 8.52 GB/sec from the chipset/memory controller to the CPU. The memory itself, running at 800 MHz data rate in dual channel (128 bit wide bus) should be able to deliver as much ase 12.8 GB/sec. There is, however, the issue of the bus utilization and as we pointed out in earlier reviews, this is one of the weakest points in the current Intel system architecture.
On the other hand, there is always the chance to overcome insufficient bus capacity (caused by an abundance of wait states) through the use of intelligent prefetch mechanisms, that is, fetching of data ahead of an actual request by the CPU. Let's take it one step at the time, though.
SiSoft Sandra memory bandwidth benchmark (buffering enabled). In short, it can only get better from here.
Cachemem
Memory access latencies, lower is better: Intel Core 2 Extreme X6800 (yellow blocks) vs. AMD Athlon FX62 (transparent blocks). The one thing that is obvious here is the impact of the large cache on the access latencies of the Core 2 memory subsystem compared to the smaller L2 cache of the AMD Athlon FX62 (AM2),
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Intel Core Duo T2600 (dual core) |
next page: => Cachemem Continued =>
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