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LOSTCIRCUITS
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| Intel's Core 2 Quad Extreme Edition QX6700 Codename "Kentsfield" | |
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(Review by MS, November 1, 2006) |
Power Issues
A major concern in die pairing are power issues. Naturally, under full load, two dies will draw approximately twice as much power as a single core. The issue, however, is not so much running under full load, rather it is the intermediate and low power states that are defining the main bulk of a CPU's power consumption. This is where selectively turning off entire portions of each die or even an entire die if it is not in use makes a sizeable difference. Keep in mind that "turning off" is a functional term to mean that the parts of the core or even the die itself go into a deep power-down state rather than being turned off completely. This technology has been used in Intel's mobile Xscale processors for years, where an interrupt service routine is used to monitor the states of CPU and requests and to make the appropriate adjustments. The adaptation of the technology into a multicore CPU results not only in a dramatic reduction in power consumption but also the same savings in heat dissipation.

Selective clock gating in a "modular" design greatly reduces idle and intermediate power consumption.
The 8MB Question
Another issue that might qualify as disconnect between marketing and engineering is the question about the L2 cache size. In terms of raw physicality, the L2 cache of the new Quad core CPU is eight MB. That is, each die with two cores features four MB L2 cache. In terms of functionality, however, the L2 cache is only four MB since the two L2 caches are not shared, and the largest chunk of data that can be stored in the "combined" shared caches is four MB. Which number is relevant for actual processing performance? Probably the latter, that is four MB regardless of the fact that there are two of them because they cannot directly talk to each other - rather they have to use the host bus and main memory for data exchange. And thus the cycle completes.
Kentsfield Specs
| Core Frequency | 2.66 GHz |
| System Bus Frequency | 1066 MHz |
| TDP | 130W |
| Brand ID | INTEL®CORE™2 EXTREME |
| Processor Number | QX6700 |
| Stepping | B-3 |
| # of CPU Cores | 4 |
| Transistor Count | 582 Million |
| Die Size (combined) | 2 x 143 mm2 or 286 mm2 total die area |
| L2 Cache | 8MB (2 x 4 MB) |
| CPUID | 06F7 |
| Core to bus ratio limit | 10:1 |
| Max processor input voltage (VID) | 1.350 V |
| PECI Enabled | Yes |
| Enhanced Intel SpeedStep® Technology (EIST) | Yes |
| Extended HALT State (C1E) Enabled | Yes |
| Execute Disable Bit (XD) Enabled | Yes |
| Intel® 64 Technology | Yes |
| Intel® Virtualization Technology (VT) | Yes |
| Package / Socket | FC-LGA775 |
| Estimated MSRP at Release | US$ 999,- |
Improved Software
When we first started looking at SMP, the only thing that really stood out compared to a single processor was the "smoothness" created by dual processing units as the prevalent user experience. Only a handful applications were SMP-enabled and - in the case of Quake3 - crashed because of speed errors. This situation has changed dramatically and new versions of truly multithreaded software are pouring into the market daily. Most of these applications center on 3D rendering or media encoding whereas there is still relatively little SMP benefit in games. The latter is not overly surprising or even relevant since only in the rarest cases, the CPU is the actual bottleneck.
At least from a technology perspective, dual processors are already old news, the latest buzz is Intel's quad-core technology showcased under controlled conditions at the last developer forum. Today we have a plethora of benchmarks showing the idiosyncrasies of the new platform supposed to take over the world.
Enter the Core2 Quad Extreme, Intel's new claim for supremacy in the world of CPUs.
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next page: => Test Configurations and Benchmark Overview =>
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