|
Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors WebNews Home |
. | . |
Prices: Mainboards ABIT ASUS Chaintech Shuttle Soyo Tyan CPU Intel P4 2.4C-800 P4 2.6C-800 P4 2.8C-800 P4 3.0-800 P4 3.2-800 AMD AthlonXP XP 1700+ XP 2000+ XP 2400+ XP 2500+ XP 2700+ XP 3000+ XP 3200+ Athlon64 Athlon64 3200+ Athlon64 FX-51 Opteron Opteron 240 Opteron 242 Opteron 244 Opteron 246 Memory Corsair Crucial Kingston Mushkin OCZ |
LOSTCIRCUITS
|
|
| Intel's ExtremeEdition P4 955 A giant leap for Intel (process technology) | |
|
(Review by MS, December 27, 2005) |
|
AMD Athlon 64 X2-3800+ (Manchester) |
Summary
Another clandestine release of another Intel flagship CPU during the last hours of the old year is unsettling the desktop world. Sporting the world's smallest transistors in an abundance of 376 million units, with 4 MB on-board L2 cache and a clock frequuency of 3.46 GHz, the new ExtremeEdition based on the Presler core is creating a bunch of new superlatives. Finally, there is an Intel processor again that can beat the AMD competition in gaming applications - and in 3dsmax - and last not least in Abbyy FineReader. But we are not really concerned about the latter too much.
Performance has its price and the power consumption of the new 955 ExtremeEdition tells a very dramatic story of Watts and frames per Watt and Watt per render pass. Finally, the energy has to go somewhere and that is more or less some heat. As always, the story is longer than two paragraphs can tell.
Sometimes things are just not going the way they were planned. I guess, everybody has one or the other experience to share in this respect, but when it comes to long-anticipated product launches, the situation can get downright awkward, particularly if the product to be launched has been declared End-Of Life even before it is released to the public. How far this particular scenario applies, is presently still not entirely clear, especially since the roadmap showing the cancellation of the Netburst architecture has not been officially confirmed by Intel.
Nonetheless, there have been doubts about the long-term viability of the Netburst architecture for quite some time, especially after the mobile processors - directly descending from the Pentium3 - have shown phenomenal performance at lower clock speed and, more importantly, orders of magnitude lower power consumption. It is not surprising, therefore, that the latest buzzword is "performance per Watt", not only at VIA-Centaur and AMD but also in Santa Clara.
In retrospect it is almost ironic that power considerations are what effectively killed the Pentium4. On the other hand, each clock cycle requires power and the P4 architecture was not developed with clock-gating in mind, once the die is powered up and clocking, there is no holding back anymore. The PentiumM on the other hand was conceived as an improved version of the PIII and every trick in the book went into the selective power management of distinct areas within the die, the "smart cache" with its selective clocking is only one example for the efforts that went into the design of this processor.
Another Christmas, another Pentium4 - codename Presler - running dual cores at 3.46GHz with 4 MB onchip L2 cache and all of that on a 65 nm interconnect process.
Conversely, in the case of the Pentium4, power management efforts have focused primarily on clock reduction of the entire die, starting with the Speedstep architecture by introducing throttling of the clock through turning on and off the master clock input. The resulting reduction in clock frequency was further increased by an on-the-fly changing of the CPU-internal multiplier and, combined with the reduced supply voltage became known as so-called EIST, short for Enhanced Intel Speedstep architecture.
A different approach was taken on the foundry level, that is, by moving to smaller interconnect processes, additional power savings were achieved. However, as by now established rather unequivocally, a smaller interconnect process is a double-edged sword. Moving to a smaller geometry naturally incurs two different issues, one of which is the smaller surface area over which heat can be dissipated, the second being the fact that a smaller process also means less distance between adjacent connections and that, in turn, means less electrical insulation between the traces - resulting in higher leakage currents.
In theory, the result is a processor or IC in general that has a relatively high power draw even under idle conditions, whereas, under full load, the overall increase in power may not be that high. SRAM cells are the next-in-line culprit when it comes to raw power consumption, however, in this case it is rather the sheer mass of 6 transistors per bit that, for example in the case of a 4 Mbyte L2 cache, add at least 216 million transistors plus overhead. Realistically, we are looking more at about 250 million transistors cycled at core clock frequency. In contrast to the PentiumM with its smart cache design, the Netburst architecture does not allow for selective clock gating of the on-chip cache, hence, whatever is there needs to be powered at all times, regardless of load on the actual execution units. The expected result is another increase in static or idle power consumption, that, however, does not increase with load.
So much for theory, we have a case in point, namely Intel's new flagship processor Pentium4 955 ExtremeEdition , codename Presler which is covertly launched at a time when every real person is either on vacation or still sick from the holidays.
|
Pentium 4 820D (dual core) |
next page: => Presler By Numbers =>
All advice and educational articles on LostCircuits are free, but if you feel you can, please make a small donation to us!