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| Intel's ExtremeEdition P4 955 A giant leap for Intel (process technology) | |
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(Review by MS, December 27, 2005) |
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AMD Athlon 64 X2-3800+ (Manchester) |
The Demise of the Single Core
Both AMD and Intel have been pushing multi-core technology in the last year. One of the biggest advantages of Intel has been the extremely low price of the entry-level model, namely, the P4 820D with an msrp of about US$230.-. Unfortunately, it appears as if the availability of this particular CPU is less than stellar, in fact, we have only found one single vendor in the Shopping.com network with this particular CPU in stock. This does not imply that there are no dual core CPUs out there, rather, the bulk is currently comprised of the 840D and and 840 ExtremeEdition that are - quite honestly - in a price league of their own. All of this is supposed to change within months to come, at least according to the latest roadmap slide.
Intel's 975 Chipset
Above is a schematic drawing of the i975 chipset. As in earlier Intel chipsets, the processor is connected to the core logic through the host or processor side bus (PSB). The latter is quad-pumped, meaning that it used two phase shifted "staggered" clocks and transfers signals on each of the rising and falling edges of both clocks. At at clock frequency of 266 MHz, this results in an overall data frequency of 1066 Mbps. Note that only the data bus is quad-pumped whereas the address and command buses are running at a pedestrian 266 MHz bus frequency. Moreover, the databus is bidirectional, meaning that data can be transmitted only in one direction at the time.
Further downstream, we have the new 82975X memory controller hub with support for dual channel DDR533 / 667 for a hypothetical bandwidth of 8.5 and 10.7 GB/sec, respectively, in dual channel mode. Keep in mind, though that the host bus with its 8.5 GB/sec will always be the limit. Arguably, there is also the possibility of DMA, meaning direct memory access by a bus master without going through the CPU. However, in this case, the master still needs to verify that the data in the main memory are valid and not cached / modified by the CPU. That means that the bus master needs to place the addresses on the bus ahead of time and wait for the HIT / HITM signal to be asserted - or rather not - before the memory access can even start. Luckily, it appears as if all current chipsets support hiding of the snoop behind an ongoing memory transfer, meaning that the cache interrogation can be done while the memory controller services the request of the busmaster in the background. Needless to say, though, that there are still substantial latencies involved, for the simple fact that the addresses and commands are subjected to a single data rate protocol. In raw numbers, every single bus occupancy translates into x numbers of CPU cycles where x is equal to the multiplier used by the particular CPU. In practice, wait states in the order of 200-300 CPU cycles or even more on initial accesses are not out of the ordinary.
All in all, the 975 chipset offers support for 22 PCI express lanes, with 16 lanes dedicated to PCI Express Graphics (PEG), that can be routed directly to one PEG slot or else split into 2 x 8 over two graphics slots. Officially Intel does not support SLI (yet), however, at least Crossfire is supposedly supported and the lack of SLI is probably more or less a matter of lockout on the level of drivers.
The ICH, formerly known as South Bridge connects to the MCH via a 2GB/sec DMI interface. Interestingly, a total of six x1 PCIe links, each with a bandwidth of 500 MB/sec are supported on top of the four 3Gb/sec SATA links, the HD audio and the USB2.0 with 60 MB/sec. In other words, the downstream connectivity exceeds the available interconnect bandwidth by approximately a factor of 2x. Keep in mind, though, that the connectivity over the DMI interface is time-multiplexed and in real life, the chances for a bus congestion are almost nil.
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Pentium 4 820D (dual core) |
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