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LOSTCIRCUITS

SHORTCUTS:
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Cache and Die Size
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Conclusion

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 Intel P4 Extreme Edition   
Cache Size Matters
(Review by MS, October 11, 2003)
Summary

THE LATEST AND MOST EXTREME EDITION of the desktop Pentium4 more than triples the transistor count to throw in a whopping 178 million transisors, cramped into a 2 MB Level3 cache. With a die size of 237 mm2, the Extreme Edition goes back to the dimensions of the obsolete Willamette but it certainly packs a lot more power to the punch.

How does this Goliath compare to the standard version? Keep in mind that there are no extra processing units, the performance boost comes from the tri-level cache architecture alone - if one does not mind using ancient AMD parlance for the Extreme Edition?

We tried to run every single benchmark in the world to show what happens but in the end, we faltered. Otherwise, we would still be at the beginning of our quest. It is a good sample, though, that we have to show what the P4EE does and what it does not and we can even explain some of it.


IN A SURPRISE BLITZKRIEG, Intel released a new processor just in time to counter the AMD Athlon 64 launch. The main distinguishing feature of the so-called Extreme Edition has been the addition of a whopping 2 MB on-die L3 cache on top of the 8kB L1 cache (+ 12 k µ-ops L1 Execution Trace Cache) and the 512 kB L2 cache introduced with the Northwood core.

With respect to the internal architecture, that is, pipelining and execution units, nothing appears to have changed from the Netburst microarchitecture introduced with the Northwood core, however, the addition of the huge Level3 cache naturally takes its toll on the transistor count and, likewise, on the power consumption.

The original Northwood core is made up of 55 million transistors. Adding 2 MegaBytes of cache, where each bit requires six transistors, to the die adds 100.7 million transistors for the SRAM cells alone. This does not include the interface logic that will take up as much as another 25 % transistor count overhead, and by the end of the equation, we are looking at the proud number of approximately 125 million transistors, only for the L3 cache - more than twice the number of transistors in the Northwood core. The total transistor count for the new processor would be ~ 180 million transistors, the number confirmed by Intel is 178 million.

One thing is rather unusual about the new core, no official name has been released for it but as far as we were able to find out, Intel's standpoint is that the new core is not a repackaged Gallatin (XeonMP) core, rather it is a Northwood with additional 8 way set associative Write-Through (exclusive) Level3 cache. It appears fair to say that most of this is a matter of semantics, just like the glass that is half-full or half empty.

next page:    => Die and Cache Size, TDP and Form Factor =>

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