|
Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors WebNews Home 
|
. | . |
Prices: Mainboards ABIT ASUS Chaintech Shuttle Soyo Tyan CPU Intel P4 2.4C-800 P4 2.6C-800 P4 2.8C-800 P4 3.0-800 P4 3.2-800 AMD AthlonXP XP 1700+ XP 2000+ XP 2400+ XP 2500+ XP 2700+ XP 3000+ XP 3200+ Athlon64 Athlon64 3200+ Athlon64 FX-51 Opteron Opteron 240 Opteron 242 Opteron 244 Opteron 246 Memory Corsair Crucial Kingston Mushkin OCZ |
LOSTCIRCUITS |
|
| Intel P4 Extreme Edition Cache Size Matters | |
| (Review by MS, October 11, 2003) |
The Cache Size - Die Size Confusion
The total die size of the Extreme Edition core has been a matter of confusion, amongst the reasons were the fact that different processors, even if they are manufactured on a similar process (e.g. 130 nm), will not scale 1:1 with respect to transistor count and die size. For example, the addition of 256 KB from the Thoroughbred to the Barton core resulted in 21 mm2 die size increase from 80mm2 to 101mm2. The transition from the Barton to the Athlon64 cannot be directly scaled with respect to cache versus die size since the integrated memory controller and the additional general purpose and MMX registers need to be taken into account as well, along with the HyperTransport interfaces. On the other hand, according to our own measurements, the 1 MB L2 cache of the different flavors of the Athlon64 occupies approximately 82 mm2 and, therefore, does scale quite well with the Barton cache size - 4 x 21 mm2 would be 84 mm2.
In the case of the Northwood core, each 256 kB block of the L2 cache takes up only 8 mm2. In other words, the cell- or bit density is approximately 2.5 x that of the AMD processors, which reflects the fact that Intel has the probably best SRAM density in the industry. If we factor this differential in memory density into any projection of the final die size of the P4 EE, that is, we take the 146 mm2 die size and add eight times 8 mm2 (8 x 256 kB = 2 MB) plus approximately 25 % overhead for the interconnect, additional, required I/O logic and interfacing, we end up with a die size of roughly 230mm2. Since a 100% utilization of real estate would end up as an extremely convoluted floor plan, there are a few empty spots on the die that can be used for additional ground planes and in so far the official die size of 237 mm2 is exactly where it should be expected.
It is actually interesting to see where the SRAM density is going at Intel. With the current 130 nm interconnect process, we are still looking at roughly 5 µm2 per SRAM cell or bit. With the upcoming 90 nm technology, the cells will shrink to a little over 1.5 µm2 per bit. As we have learned, Intel has already produced 52 Mbit SRAM arrays, including all additional logic and I/O functionality, which, in accordance with our numbers about a roughly 25% overhead, results in approximately 330 million transistors on as little as 109 mm2. This means that in the next generation of CPU, we may see as much as 6 MB L3 cache including ECC functionality on the same 100 mm2 footprint.
Electron Micrograph of a 6T-SRAM cell manufactured using a 90 nm process, picture courtesy of Intel.
next page: => TDP and Form Factor =>
