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LOSTCIRCUITS	SHORTCUTS: Hafnium Transistors and Gates Penryn Details A short Transistor Tutorial Give Us Some Feedback on this Review
Intel's Penryn Core Putting the Metal Back into CMOS
(Author: MS, January 28, 2007)

Process Intricacies

Intel uses atomic layer deposition (ALD) of Hafnium for the formation of the High -k layer to insulate the gate from the substrate. ALD allows for precision control of layer thickness which is similar to chemical vapor deposition but makes atomic scale deposition possible because of the self-limiting nature of the uniform film growth. ALD is conformal and pinhole-free with layer thickness as fine as 0.01 nm possible per monolayer - a prerequisite for precision control of field-effect and insulation strength.

The biggest advantage in the current process is the combination of a high field effect (high-k) that allows increased thickness of the insulator and use that increased thickness for better insulating properties. In the current implementation, Hafnium alloys and metal gates used in the Penryn processor result in what Intel calls a breakthrough technology in transistor technology at 45nm lithography, based on a combination of high-K (Hafnium insulator) and metal gate electrodes. In short, the combination of the process shrink with the high-k dielectrics and the metal gates is supposed to result in an increase in the switching speed of the transistors by more than 20% at a 30% reduced switching power.

We have a short transistor tutorial as appendix to this article

To make matters even more compelling, the leakage power of the transistors has been reduced by a factor of 5x for the source-drain leakage and more than 10x for the gate oxide leakage power. As we described in several earlier articles, leakage currents were threatening to end the downscaling of process technology with a cut-off size of about 60 nm. Hafnium alloys as insulator with their more than 10 x improved insulating properties will finally allow the migration to yet smaller process technologies. All of this is achieved using the P1266 process using dry lithography at 193 nm wavelength. It is obvious that the P1266 process will be the last step in the long legacy of dry lithography, the next scaling down to 32 nm will - with a very high probability - switch over to immersion lithography. Nevertheless, compared to the 65nm process currently used, the 45 nm process allows the accommodation of approximately twice as many transistors in the same area.

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