Intel’s 32 nm CPUs: The Westmere Family - Launch in Q4 2009
Today Intel unveiled the first working processor based on the new P1268 process using immersion lithography on critical layers with 9 layers low-k copper interconnect. Interestingly, the manufacturing process uses immersion only on some of the layers – described as critical – which comprise the actual NMOS and PMOS whereas the interconnects apparently are still done in a dry lithography process.
The migration to 32 nm is the typical “Tock” in Intel’s Tick-Tock development model where every 2 year’s Tick is the introduction of a new architecture based on the existing process technology, followed in the next year by the “Tock” of migrating to the next design process. What sets Intel apart from AMD and other semiconductor companies is that all tools and processes are developed internally, making Intel independent from fluctuation in the market or – good will of partners.
In short, the high-lights of the 32 nm technology are:
- 2nd generation high-k in combination with metal gate transistors
- 0.9nm equivalent oxide thickness high-k(
(scaled from 1.0 nm on 45nm process)
- Replacement Metal Gate process flow
- 30nm gate length
- 4th generation strained silicon
- Immersion lithography on critical layers
- ~70% dimension scaling from 45 to 32 nm process
- Pb-free and halogen-free packages
The results are:
- > 22% performance increase
- tightest reported gate pitch
- highest reported drive currents
The new process is actually two different processes depending on the target design, that is, the 1268 process is optimized for performance and will be used for CPU manufacturing. At the same time, the 1268 process was adapted towards highest power efficiency as used in System on a Chip devices (SoC), that takes into account higher levels of I/O logic and integrated memory, both of which have slightly different manufacturing requirements than straight core logic.
picture soc
The next Generation CPU Line-up: Nehalem and Westmere Decoder Ring
| &nbst; | Segment | Nehalem (45nm) | Westmere (32nm) |
| Desktop | High End | Bloomfield (4C/8T) | Gulftown (6C/12T) |
| &nbst; | Mainstream | Lynnfield (4C/8T) | Clarkdale (2C/4T +iGFX) |
| Mobile | &nbst;
4+ Sockets | Clarksfield (4C/8T) | Arrandale (2C/4T +iGFX) |
| Server | Expandable Scalable
4+ Sockets | Nehalem EX (8C/16T) | Future Westmere based CPUs |
| &nbst; | Efficient Performance
2+ Sockets | Nehalem EP (4C/8) | Future Westmere based CPUs |
| &nbst; | Efficient Performance
2+ Sockets | Nehalem EP (4C/8) | Clarkdale (2C / 4T +iGFX) |
The projected launch date for the first Westmere CPUs is Q4 2009, which, given the yield analysis and rapidly declining defect rate appears to be very realistic.
Westmere CPU details
Westmere is essentially a re-sized Nehalem design manufactured on the P1268 process in 32 nm geometry. In a nutshell, the key features are:
New Multichip Package
The same package will feature two separate dies, namely, the actual CPU or multicore processor manufactured in 32 nm and the IGP with integrated dual channel memory controller based on a 45 nm design. The reason for mixing two different process technologies is that the 32 nm CPU is already ready for primetime whereas the IGP was just ported from 65 nm to 45 nm. As soon as the 32 nm transition is completed also for the IGP/IMC, the 45nm part will be replaced with its 32nm counterpart. We don't have details on the architecture of the IGP but the note about the scaling from 65 to 45 nm technology suggests that there will be no radical changes from existing Intel IGPs to the new GPU. The two dies are connected via a QPI link. Note that there will be no more triple channel memory support, rather, the memory interface will be a conventional dual channel DDR3 memory controller
The CPU die features new SSE4.1 instructions, specifically AES (Advanced Encryption Standard) instructions, a 4 MB L3 cache and is capable of Hyperthreading. Interesingly, there are no listings for any quad-core CPUs, everything is going back to dual cores with HT for four logical processors with the exception of Gulftown featuring 6 cores and 12 threads. Power consumption was disclosed to be in the same thermal envelope as existing Intel CPUs, with the Westmere design delivering substantially higher performance than existing 45nm processors.
Steve Smith: Westmere
4 different fabs over the next 2 years $8 billion
Accelerated product ramping
Going forward with the process cadence (Tick-Tock Development Model: New architecture followed migration to a new process
Desktop and notebook demonstration
Future server products as well
Westmere: Nehalem in 32 nm process
Smaller core with increased performance and power flexibility important for power-constrained e4nvironments
Gulftown as 6 core version
Server: single =-socket: Clarkdale
Westmere: 2 and 4+ socket servers
Lynnfield / Clarksfield (desktop/mobile) 45nm
Clarkdale / Arrandale (desktop / mobile) 2 core/4 thread (HT) integrated memory controller
X58 platform : HEDT: Gulftown 6C 12T processor HEDT High End DeskTop
Piketon/Kings Creek Platform: Lynnfield (desktop) => Clarkdale 2C 4T
š Future Sandy Bridge
Xeon:
Boxboro
Tylersburg
Foxhollow (5 series chipset)
Nehalem EX 8 core 16T
Mainstream Client platform Repartitioning
Penryn: 3 chips = westmere: 2 chips
Westmere: 2 chips one package 32+ 45nm dies on one package
Flexibility for manufacturing (graphics from 65 to 45 nm (now) and later to 32 nm) Accelerated CPU as first step.
2 different implementations: Lynnfield 4 core 8T monolithic no integrated graphics
Clarkdale 2 core 4T + separate graphics chip on same package QPI interface, more variability and tweakability. Memory controller on graphics die
De-prioritization of Havendale
AES advanced Encryption Standard SSE 4.1
arrandale