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LOSTCIRCUITS	SHORTCUTS: Out of Copenhagen Test Configurations Memory Subsystem Power Consumption 3D Rendering Energy Efficiency Cinebench AV Encoding: DVD-Shrink, DrDivX, MainConcept AV Encoding: Virtualdub / DivX and SSE4 Gaming: 3DMark '06 FarCry F.E.A.R. Overclocking Final Words Give Us Some Feedback on this Review
Intel's Penryn Core Turns Yorkfield at 3.0 GHz P1266 at 45nm, 12 MB L2 Cache, and SSE4 Instruction Set
(Review by MS, October 28, 2007)

Memory Performance

We used SiSoft Sandra to measure memory bandwidth available to the CPU. Obviously, it is more a matter of the chipset than the CPU but the migration to DDR3 does increase bandwidth - even if we were running within the envelope of the officially supported host bus interface frequency ... at officially not supported 6-5-5 latency settings.

Buffered Memory Bandwidth. Since a total of 4 cores needs to have access to data over a shared bus, it is important that enough bandwidth is available. For correlation with any real world performance, it is also important to factor in prefetch algorithms based on e.g. Intel's smart memory management strategies as it is done by enabling buffering/prefetch in the benchmark.

Overall, the test system scored remarkably well, being bested "in-house" only by the obsolete Prescott core-based P4 XE at 3.73 GHz. Needless to say that a bunch of AMD configurations achieve better memory scores, particularly if cache coherent Non Uniform Memory Architecture is allowed to play out its forte.

Cache Latencies

Whenever there is a larger cache, there is the instant assumtion that the increase in size has to come at the expense of access latency. The answers are not always trivial, different benchmarks lead to different results even if the results are correct and not based on erroneous readings of the timestamp. We have used Cachemem 2.65 in the past and the theoretical results always matched well the observations in real world scenarios, reason enough to use the same tool again and see what it reports. Also necessary to keep in mind is that different block sizes will result in different access latencies, even if they fit inside the one or other cache. For the case in point we are using two block sizes, namely 2048 and 4096 KB that, at first glance, give slightly different results, but are essentially identical with respect to showing cache access speed of both CPUs. The blue lines with the red markers are the values for the QX 9650 (Yorkfield) whereas the green lines with the orange markers represent the QX 6850 (Kentsfield).

Cache access latency cycles depending on stride length: lower is better! The two performance graphs of the QX 6850 came out as the "best" and "worst" whereas the QX 9650 is right in between. Bottomline here is that there is no increase in L2 access latency from Kentsfield to Yorkfield, if anything, Yorkfield is actually faster. All L1 latencies were identical for all runs of both CPUs.

(BX80557E6300)

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