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| Low Power and Energy-Efficient CPUs from Intel and AMD Core2 Duo E6300 vs. X2-3800+ (ADD) and X2-4600+ (ADO) | |
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(Review by MS, August 20, 2006) |
Memory Subsystem
One aspect of the memory subsystem in the Core2 Duo that was somewhat puzzling was the relatively low performance in terms of raw bandwidth - particularly when compared to the excellent performance in memory-intensive applications. We had some discussions with a few of Intel's engineers about this phenomenon and the short version is that the controller attempts to perform a logical analysis of the memory traffic and then applies very targeted prefetch algorithms to the memory traffic. In good old industry fashion, the technology has a new name: Memory Disambiguation. In essence, disambiguation is similar to nVidia's DASP technology introduced with the nForce chipset but since it is done on the level of the CPU rather than on the chipset, it is more effective. In fact, Intel claims that the Core2 Duo processors can utilize a single bus idle cycle to optimize memory traffic and that, under these conditions, no other CPU-memory subsystem can compete with their efficiency.
For the time being, we still use a more conventional approach, namely SiSoft Sandra 2007 and Cachemem 2.65 to look at raw, unadultered bandwidth and access latencies.
As not expected otherwise, the AMD memory subsystem is heavily dependent on the CPU clock speed. However, since the memory clock is derived by dividing the CPU clock speed by an integer number, the 4600+ using a 1/6 divider runs the memory clock at 400 MHz, whereas the 5000+ has to use a 1/7 divider which results in a 371 MHz memory clock. Consequently, the 4600+ offers better memory performance than the 5000+. In the case of the Core2 Duo processors we also note a slight dependency on clock speed but it is negligible compared to the AMD systems. Needless to say that the ccNUMA enabled Dual Opteron system still holds the record here.
Cachemem 2.65: Core2 Duo E6300 vs. E6700
For starters, we are looking at a comparison between the E6300 and the E6700.
Aside from the smaller cache causing higher access latencies in the 2-4 MB data block size passes, the 6300 (transparent blocks) also shows slightly higher latecies across the board compared to the E6700. With respect to the cache, this is not surprising - after all, cache access latencies are usually defined as CPU cycles, and, therefore, a higher CPU clock frequency will result in faster cache accesses. At the same time, the memory management unit (MMU) of the CPU abides by the same rules, which explains the overall slightly elevated latencies even for main memory.
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Athlon64 X2-3800+ (ADA3800DAA5CD) | |
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Core2 Duo E6300 (HH80557PH0362M) |
next page: => Memory Subsystem II. =>
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