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Intel is finally launching the successor to the original Willamette-core based Pentium4. The core has been in mass production since May of last year with a total of six factories planned during 2002. Major revisions of the CPU include a die shrink from 217 to 146 mm² achieved by using 130 nm copper interconnect instead of 180 nm aluminum technology. The the shrink technology is supplemented by 60 nm channel legth transistor technology expected to scale up to 3-3.5 GHz in the near future. With respect to layout and features, the main distinguishing feature is the increased 512 kB 8 way set associative L2 cache. Clock by clock, the Northwood literally crushes the Willamette core in performance and with the higher speed grades it is a serious CPU with low thermal load. In the end, though, AMD's new Athlon XP2000+ still wins most of our benchmarks.

The new Northwood core-based P4 arrived in a Socket 479, no reason to panick, though as our friends on [H]ardOCP found out that those were just some parts conveniently sitting in the warehouse. In other words, there is no reason to be afraid that Intel will move to a new interface within the next few months. As in the case of the older Willamette core based CPUs, the core is embedded in a full metal jacket to allow controlled disspation of heat into the environment / heatsink. The marking on the metal slug shows that aside from the 2.2GHz clock speed, a 512 kB on-die full speed L2 cache is the distinguishing factor of the Northwood core

Very briefly, the P4 architecture is characterized by its 100 MHz quad pumped bus interface delivering a virtual 400 MHz or, in technical jargon, 400 Mbit / sec and pin bandwidth. The data are funneled into a 20 stage pipeline towards the execution units that are either the two double pumped integer or Arithmetic Logic Units (ALU) or else to the single Floating Point Unit that is, however, blessed with double the width of a standard FPU, namely 128 bit. In plain English, this means that:

• At 400 MHz, the FSB delivers up 3.2 GB/sec bandwidth to the system core logic.
• The extra-deep branch prediction / recovery pipeline (20 stages) is twice as deep as the one in the Pentium 3 (10 stages) which allows to ramp up clock speed since the data are chopped up in smaller chunks that require less time to process. Conversely, any miss will result in a 20 cycle penalty.
• two ALUs working at twice the clockspeed each are roughly equivalent to four individual ALUs (Rapid Execution Engine)
• A single 128 bit wide FPU can execute one double-precision (128 bit) SIMD, two double precision (64 bit) FPU operations simultaneously or else four single precision (32 bit) operations per clock cycle.
• The execution trace cache is a level 1 cache that stores approximately 12k decoded micro-operations, which removes the decoder from the main execution path, thereby increasing performance
• The Willamette core features a 256 kB Advanced Cache Transfer (ACT) L2 cache running at full speed.
  • ACT means that the L2 is 8 way set associative and interconnected with the core logic via a 256 bit (32 Byte) interface with data transfers on every clock cycle for 51.2 GB/sec at 2 GHz clock frequency. If I understand this correctly, this is a substantial step-up from the Coppermine L2 cache operating in back-to-back mode, meaning that data transfers only occur on every other clock cycle.
• SSE2 (Internet Streaming SIMD Extensions 2): The P4 introduced 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase.
• Data Prefetch Logic: Based on the locality of data in the memory space, adjacent blocks of data are preloaded into the cache to be available if needed. Prefetching can greatly increase application performance.

A major criticism about the Pentium4 processor has been its power demand and the associated thermal load established in the industry as the "Gelsinger Paradigm" or "How many P4s does it take to heat an appartment?". At its introduction, running 1.5 GHz, the P4 was rated at 52W heat dissipation and, assuming that power draw scales almost linearly with frequency, this means that at 2.0 GHz the original Willamette core will produce no less than 70W of heat. Needless to say that the competition has not been sleeping and any current high-end AMD CPU will be in the same thermal ball park.

Related to the rather immense power draw has been the fact that at 180 nm interconnect technology, the 42 million transistors resulted in the Behemoth die size of 217 mm2. A general rule of thumb in the IC business is that, above 100 mm2 die size, it is increasingly difficult to maintain profitability. Wafer prices are high and the number of dies from one wafer is reciprocal to the die size. Specialty ICs or even high-end processors are exempted from this rule but most "commodity" parts, including a mass-produced CPU will become "golden" only around 100 mm2. I have been assured, though, that even at 106 mm2 die size, the Coppermine makes money for Intel.

Taken together, the power consumption / heat dissipation and the wafer costs are enough incentive to develop a new technology and Intel made a quantum leap here to jump right ahead to 130 nm using copper for the metal layers instead of the aluminum used in the Willamette core. A new interconnect, however only partially solves the issues at hand and can only work with a new breed of transistor, meaning that the functional units of the CPU needed the makeover as well.

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