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LOSTCIRCUITS	SHORTCUTS: Willy, Woody and Scotty Coolers R'Us Enhanced Power Management Specs and Names testConfiguration NX vs. DX Memory Bandwidth Latencies WorldBench5 -1 WorldBench5 -2 3dsmax More 3D Rendering Cinebench2003 Gaming FutureMarks Conclusions Give Us Some Feedback on this Review
Intel Pentium4 600 Series
(Review by MS February 21, 2005)

Summary

Instead of using a major sports event to compete for attention with the latest product launch, Intel did move to the small hours of Sunday of the President's Day weekend for a clandestine introduction of the latest 600 series of P4 processors. The new and improved core features a number of nifty improvements in the form of Enhanced Power Management, EM64T support through added registers and last not least doubling of the L2 cache size to 2 MB. We will take it step by step to go in 31 pipeline stages over the new features and the performance impact on different types of applications. The net result is neither surprising nor earthshaking but suffice it to say that at equal pricing, the new 600 series appears a better choice than the original LGA775 Prescott 500 series.

First there was Willy, then there was Woody and now we have Scotty. Willy sucked, Woody was a hero but somebody thought there was a need for Scotty. And Scotty never made the splash that Woody made. So if Woody was better than Willy and Scotty was better than Willy, how many transistors does it take to fill 135 mm²? The answer is easy, it depends on the process, and at 90 nm interconnect, it is possible to squeeze some 169 million transistors into that area.

Aside from the actual core with the decoding and scheduling logic, not to mention the registers, the original Prescott featured 1 MB of Level2 cache along with the 16 kB data cache, all of which added up to some 112 mm² containing 125 million transistors. One MB of cache alone occupies 6 transistors per bit times 8 bits per byte or in plain numbers, approximately 48 million transistors. Therefore, adding another 1 MB of cache would increase the transistor count to approximately 170 million transistors, which is approximately, what the latest and greatest Scotty2 features.

Interestingly though, adding transistors does not necessarily reflect in the overall die size. In fact, one of the greatest strengths of Intel’s design team has been to shrink the transistors building the SRAM cache to dimensions that make everybody else green with envy. In plain numbers again, adding 48 million transistors can be accomplished at a record-low die size penalty of only 23mm².

Prescott and P4 6xx series dies side by side (1: Execution Trace Cache; 2: L 1 Data Cache with muxer (pink); 3: 512 KB L 2 cache blocks; 4: L 2 tag cache)

Click for full size picture!

What we are getting at is that in term of actual wafer costs, adding some extra cache comes relatively inexpensive for Intel. At the same time, adding cache has been an established way to increase performance of any processor, at least in certain applications. And then, there were some other issues that needed to be addressed, particularly the long overdue debut of 64-bit capabilities which, admittedly, only really requires a few additions to the internal registers of the processor, which, rumor has it were there in dormant form from the beginning of Scotty.

Likewise, in the day and age of heightened security requirements, it appears necessary to add what is commonly known as the so called no-execute bit (NX) or in Intel parlance DX for deny execution. This DX bit addresses one vulnerability of virtual memory addressing, specifically the fact that the OS sets the code segment to cover the entire memory address space, regardless of whether the addresses contain data or instructions. This general execution permission can be exploited to force execution of instructions disguised as data at the highest privilege level. More details on this in our investigation of the NX bit

Suffice it to say that in the long run, Intel could not afford to ignore the precedent set by AMD with the implementation of the DX bit, especially with Microsoft adding support within Service Pack2 of WinXP and all of their 64-bit operating systems. As we mentioned in our article on the NX / DX bit, implementation of the relevant changes in hardware is relatively uncomplicated, the only requirement is the addition of a switch for bit 63 in the paging table entry with the possibility of setting it to 0 or 1 for allow execution or deny execution, respectively.

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