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LOSTCIRCUITS	SHORTCUTS: Willy, Woody and Scotty Coolers R'Us Enhanced Power Management Specs and Names testConfiguration NX vs. DX Memory Bandwidth Latencies WorldBench5 -1 WorldBench5 -2 3dsmax More 3D Rendering Cinebench2003 Gaming FutureMarks Conclusions Give Us Some Feedback on this Review
Intel Pentium4 600 Series
(Review by MS February 21, 2005)

Enhanced Power Management

Briefly, Intel's Enhanced Power Management features three different mechanisms that all resort to the same transistors and capacitors to accomplish reduction in power consumption and heat dissipation. What is different, though, are the mechanisms used to accomplish power management. The three mechanisms are:

• C1E or Enhanced Halt State
• EIST or Enhanced Intel SpeedStep Technology
• TM2 or Thermal monitor2

C1E or Enhanced Halt State

With the P4 500”J” series, Intel introduced a new version of the C1 HLT state that is induced as soon as the operating system issues an idle loop instruction. A typical halt state is defined as turning off as much as 90% of the clock input under idle situations. In general, the idle loop itself can be used as the instruction to trigger the halt state, however, in situations of heavy load, correct execution of the low power state may require an interrupt service routine that appears part of WinXP SP2 to warrant better granularity.

The new enhanced version, appropriately dubbed C1E builds on the existing mechanism but, in addition, changes the multiplier setting of the processor to the lowest possible value and subsequently changes the CPU voltage via VID. The result is a substantially lower power consumption than that accomplished with C1 alone. In other words, where C1 only turned off some of the CPU internal clocks, C1E changes the clock frequency and the supply voltage before turning off the clocks.

Thermal Management as it used to be with the drawback of severe stuttering upon assertion of the STOPCLK bit triggered by the PROCHOT signal on the left. Shown on the right is the new TM2 technology that works primarily via multiplier changes alongside with the appropriate dynamic voltage scaling. The same mechanism is used regardless of whether power management is triggered by C1E, EIST or TM2.

EIST or Enhanced Intel SpeedStep Technology

The same hardware is used to invoke the Enhanced Intel SpeedStep technology, however, the difference is that EIST uses the Operating Systems load monitor (Ctrl-Alt-Del => Performance) to toggle between frequency and power states. The frequency changes are managed via ACPI and require OS and BIOS support.

TM2 or Thermal monitor2

Going down memory lane to dig out the different inceptions of Intel’s thermal monitors generally unearths some ½ dozen of different thermal diodes, TCCs and whatever names were featured on the tabloids on the day where a new term needed to be created. Up to now, the mechanism used to prevent overheating of the processor included the thermal control circuitry that would use the PROCHOT (as in Processor Hot) to assert the STOPCLK signal and turn off the internal clocks of the processor for an amount predefined as a multiple of 12.5% of total processor clock with the interval itself being limited to no more than 3 msec. The result of the TM1, short for thermal management 1, was the typical stop and go of processor activity as shown in the figure below. TM2 uses the same hardware as that used by C1E and EIST to lower power consumption, that is a frequency modulation concomitant with the necessary voltage adjustment. The result is that instead of changing the net clock cycles over time (which still could be construed as a change in frequency) the 600 series does a real frequency change via multiplier adjustment as soon as the temperature reaches a critical point along with the reduction in supply voltage through dynamic voltage identification.

The implementation of the dynamic voltage identification is a key player in the reduction of leakage currents, that is, lower voltages will result in lower leakage across the insulating substrate. In turn, this will result in lower die temperature and, consequently, in lower cooling requirements.

One trivia to mention here, not because it is obvious but despite that fact, is that the latest Extreme Edition does not feature Enhanced Power Management. Obvious it is because, as we showed in several past articles, the Prescott core does not support multipliers lower than 14x. Since the Extreme Edition uses a 1066 MHz processor side bus frequency, it needs to use this very lowest multiplier setting to accomplish the 3.73 GHz. In other words, the Extreme Edition already uses the lowest multiplier possible and that means, it cannot go lower than that – ergo, no Advanced Power Management.

EM64T

With that much power play, it is easy to overlook the issue that the 600 series features 64-bit Operating System capability. That is, it is possible to run WindowsXP-64 or any other 64-bit operating system that is compatible with the system architecture with all known benefits such as capability to address more than the conventional 4 GB of memory. Keep in mind that 4 GB of system memory means that a maximum of 2 GB can be allocated for applications, the rest is reserved for the operating system unless the 3GB switch is set in the Windows.ini file. In order to accommodate 64-bit computability, the number and size of the internal registers had to undergo some changes, that is, the original eight 32-bit registers were extended to 64-bit and in addition, the number of SSE and integer registers were doubled from eight to sixteen each. All in all, this results in a doubling of the internal registers – which, from a performance standpoint are probably the most critical parts of the memory subsystem within any processor. Keep in mind, though that only a 64-bit OS will be able to use and take advantage of the extra registers. For 32-bit OS environments, registers will be business as usual, that is, only the lower block of the 64-bit registers will be used, likewise only 8 each of the SSE and Integer registers are useable.

SSE3 Instructions

Not a new feature but amongst the hilights of any Intel presentation ... and about as exciting.

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