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We used SiSoft Sandra Memory Benchmark to measure the overall bandwidth between the system memory and the CPU. What we were mostly interested in was where the critical bottlenecks are. That is, how much gain will there be moving from a 400 MHz FSB and PC2700 DDR to a 533 MHz FSB with PC2700 DDR. The same goes for the i850 chipset, that is 400 MHz vs 533 MHz FSB combined with PC800 and PC1066 RDRAM in all possible combinations. Last not least, take all data for DDR and RDRAM and compile them into a single chart.

Prelude: Buffering enabled, PC1066 RDRAM, 533 MHz FSB.

Buffering Enabled

Integer (red) and Floaing point (grey) bandwidth. 2.4 = 2.4 GHz, 2.53 = 2.53 GHz; -100, -133: FSB; /SPD: DDR333 at SPD settings; /800 PC800 RDRAM; /1066: PC1066 RDRAM; /146: The 2.53 GHz P4 was overclocked to 146 MHz FSB / 183 MHz DRAM frequency (2775 MHz) on the ASUS P4S333. With buffering (prefetching) enabled, streaming memory bandwidth is largely independent of latencies because of early read commands for DDR and staying in page, meaning that page miss latencies are becoming a negligible factor.

At 100 / 400 MHz FSB, differences between the DDR and the Dual Channel Rambus platform are only minor and, likewise, the differences between PC800 and PC1066 RDRAM fall in the noise. Since the memory and FSB are the bottlenecks here, different CPU multipliers do not affect the bandwidth. Interestingly, also increasing the FSB from 100 to 133 MHz or 400 to 533 Mhz data rate only marginally increases the bandwidth on the DDR platform since the memory bus itself becomes the primary bottleneck.

Moving to the 133 MHz FSB in combination with RDRAM, however, "opens up the gates" for much higher yields than even running PC1066 on a 100 MHz FSB. The combination of PC1066 RDRAM and a 133 MHz FSB results in about 50% higher bandwidth than the 100 MHz FSB / DDR333 combination.

Buffering Disabled

Integer (red) and Floaing point (grey) bandwidth (legend see above). With buffering (prefetching) disabled, latencies play a much bigger role. In this case, it appears as if chipset latencies at the 133 MHz setting of the SIS 645 chipset are the biggest problem since the P4 2.4B falls behind the 2.4 on the DDR platform. On the other hand, the dual channel RDRAM interface provides a huge pipe for data and clearly wins this competition.

As always, the disclaimer is that SiSoft Sandra is not necessarily an indication for the performance level in real world application.

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