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Performance rather than clock speed must have stood godfather for the new HyperThreading technology introduced by Intel only a few days ago. Taking advantage of unused CPU cycles is something we got accustomed to when running Distributed.net RC5 clients. Now Intel is seriously attempting to spoil the fun by enabling other applications to thread into the void spaces like a well-greased zipper. Good thing that RC5 is history by now. There have been speculations, benchmarketing and overall a lot of confusion over HyperThreading. We are taking our own shot at what is going on with the new technology, what is the penalty in production and in performance in non-optimized applications and how much we can expect under optimal conditions. We even have some insights as to what "optimal conditions" means. Read on ...

A few days ago, Intel released the latest addition to a rather impressive CPU repertoire to include the 3.06 GHz P4, raising the clock speed just another notch. In general, though, the hardware community has reached a certain agreement that clock speed does not necessarily equal clock speed, which translates into ratings based on performance. The best known example is AMD's QuantiSpeed rating based on instructions per clock (IPC).

Aside from radically different processor designs and platforms, there are other instances where performance will depend on more than just raw clock speed. The main concept is to make more efficient use of the individual processing units, that is, to thread the individual workloads through all stages in the processor to optimize the overall number of executions / clocks. No process without a name, in this case, the term Simultaneous HyperThreading was coined.

The power of HT was wrought upon us in its usual confidential disguise.

HyperThreading

What is HyperThreading anyway and why would anybody actually need it? Very briefly, Simultaneous HyperThreading or HT (SHT sounds like .. ) is a pseudo-substitute for symmetric multiprocessing (SMP) technology where, instead of having two CPUs, a single processor internally creates two virtual or logical processors. The idea behind HT is that handling data and instructions from two different applications in parallel rather than in a serial fashion will fill the gaps that naturally occur in the execution of either application with workload from the second application. As a result, the processor will be fully utilized rather than working in a stop and go fashion.

The words "parallel" and "simultaneous" are somewhat misleading here since true parallelism would include that everything is processed simultaneously through two parallel pipes. A more appropriate picture would be a zipper where data chunks from two parallel instruction sets are processed in alternating chunks by interleaving data and instructions. On a processor level, this would mean that the CPU continuously switches from one application to the other in a few nanoseconds intervals. The problems associated with this technology are that additional buffers are required for holding the data internally and for keeping record of the status of each set of instructions.

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