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LOSTCIRCUITS	SHORTCUTS: Top Page Strained Silicon Die (re)Organization Prescott New Features I Prescott New Features II Test Setups Latencies Sysmark 2004 Internet Content Creation Office Productivity 3ds max 5.1 Amorphium Cinebench 2003 D3D Gaming => OpenGL Thermal Issues Overclocking, Final Words Prescott 3.0 Pricing Give Us Some Feedback to Improve our Reviews
Intel Pentium4 "Prescott" Strained to the Silicon
(Review by MS, Feb. 1, 2004)

From a manufacturing standpoint, achieving 90 nm technology is something that only five years ago was thought to be almost impossible. In trivial terms, the major shortcomings are the wavelength of the light that is used to expose the wafers behind a photomask as well as the issue of limited conductance with decreasing thickness of any material that can be used in microchip technology. In other words, even with the most sophisticated masks and using deep UV light at 193 nm wavelength, which is far below the range visible by the human eye, it is not possible to selectively expose traces of the kind of thickness we are looking at here. The work around the laws of optics that cause bending of light rays at the edge of any mask is to use differential interference contrast. That is, waves of light, if they are superimposed, will cancel each other out or else amplify each other. This way it is possible tp create shadows and lights that are beyond the resolution of the photomask. The details are far outside the scope of this article but suffice it to say that the lithography used to create e.g. the original Intel Pentium Classic or AMD K6 appears like cave-painting in the stone age compared to what is used for the manufacturing of the Prescott masks and die. This is only the beginning, the next step in process technology will move to "Extreme UV" at a Lambda of less than 13 nm in 2009.

Strained Silicon

The above mentioned manufacturing issues aside, the next problem is that any electrical conductor is bound by a different set of the laws of physics in that the propagation of electrical information requires a minimum amount of conductance, e.g. across a transistor gate. The thinner the gate substrate, the lower will be the conductance; consequently, the signal velocity will drop, even if the gate length is reduced in a proportional fashion. Electric current, however, is noting but the transfer of electrons from one atom to another within a lattice of conductors or, by extension, semiconductors. Only the electrons of the outermost shell of each atom can be transferred and the "jumping" of those electrons is facilitated if the array of the nuclei is subjected to deformation or strain. That is, the nuclei are either spaced further apart from each other (tensile strain) or pushed together (compressive strain). In other words, if any given substrate or lattice is stretched or "strained", the internal resistance of the substrate will be lowered and the flux of electrons through the "maze" of atoms will face lower resistance.

                    

The original IBM approach to strained silicon places the silicon over a SiGe lattice which results in "stretching by passive alignment". One of the side effects is that the silicon is stretched along both axes as shown in the second picture (courtesy of Intel) as "Traditional Approach". The same slide shows the techniques used by Intel to induce a uniaxial tensile strain (nmos devices) or compressive strain (pmos devices). In the case of the pmos transistors, a post etching fill with SiGe is used which is then compressed using a nickel-silicide deposite (third picture, courtesy of Intel). In the case of an nmos transistor a tensile Si₃N₄ cap is applied over the actual gate, which pulls the gate apart and, thus, mechanically stretches the silicon (fourth picture, courtesy of Intel).

On June 8, 2001, IBM publicly announced the discovery of a new form of silicon, dubbed strained silicon. Strained or stretched silicon is based on the discovery that silicon atoms have a tendency to line up with each other. If a "relaxed "substrate is created by mixing some 15% of germanium into the silicon, the spacing of the silicon atoms is about twice as wide as in a pure silicon lattice. If a standard silicon substrate is placed over the relaxed silicon, the silicon atoms in the first will still try to line up with the relaxed lattice, thereby arranging themselves in a looser formation than without being put on the "stretcher". The result is an increase in conductivity by up to 35%, which translates in a 35% higher signal velocity across the gate and, hence, is one of the prerequisites for achieving higher clock speed.

Every microprocessor uses two different types of transistor, that is the nmos transistor that is conducting at high voltage at the gate and the pmos transistor that is conducting if the gate voltage is low. Together, the two types of device complement each other to warrant most power-conserving operation, therefore, an array containing both n- and p-mos transistors is called CMOS with C as in complementary. Empirically, it has been found that the nmos transistor gates are conducting better if a tensile strain is applied, whereas pmos devices operate better using a compressed gate silicon. Therefore, it is only a small step (at least conceptually) to implement two different technologies to exert a tensile strain using a tensile cap that pulls the gate apart, or else a compressive strain using Nickel Silicide to compress the epideposite of the GeSi lattice at source and drain.

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