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| Intel Pentium4 "Prescott" Strained to the Silicon | |
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(Review by MS, Feb. 1, 2004) |
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Intel Prescott Starting at: |
In the description of the changes entailing the release of Prescott, we mentioned the different organization, design and size of both the Level1 and Level2 cache. It does not come as a longshot to assume that differences mentioned, especially the changes in set-associativity will reflect one way or the other in different access latencies as well. Instead of our famous dual 3D-plot of the different access latencies, we applied Occam's Razor for clarity reasons and confine ourselves to a section through the 3D plot using the 1MB stride lenght for the standard Northwood, the P4EE and finally the Prescott to look at overall access latencies and then to focus on the different levels of cache.

Access latencies in number of clock cycles for the Northwood (yellow), the ExtremeEdition (pink) and the Prescott (blue) using the same system. The different cache sizes cause different onset points for the increase in access latency for the three processors. However, also the latency when accessing the main memory is slightly different for the three CPUs with the Prescott being the slowest of the three.

Same data set as above but zoomed in on the transfer sizes that fit into the L1 / L2 cache in all three CPUs.
Where Cachemem reports a single cycle access latency for the Extreme Edition and the Northwood, it is no less than 4 cycles for the Prescott. Likewise, the number of clock cycles needed to access the L2 cache is about 50% higher in the case of the Prescott than in the case of the Northwood / ExtremeEdition, however, the amount of data that can be handled by either L1 or L2 cache is twice that of the Northwood or Extreme edition. This warrants low latency data access over a broader range of application. That is, whenever the total amount of data that is needed is between 8 and 16 kB or 512 and 1024 kB, respecitvely, the Prescott will have the lowest latency accesses and will, therefore, be the fastest of the three (at the same clock speed). Coincidentally, the L2 access latencies are almost identical to the pipeline length in each of the processors.
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