|
Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors WebNews Home |
. | . |
Prices: Mainboards ABIT ASUS Chaintech Shuttle Soyo Tyan CPU Intel P4 2.4C-800 P4 2.6C-800 P4 2.8C-800 P4 3.0-800 P4 3.2-800 AMD AthlonXP XP 1700+ XP 2000+ XP 2400+ XP 2500+ XP 2700+ XP 3000+ XP 3200+ Athlon64 Athlon64 3200+ Athlon64 FX-51 Opteron Opteron 240 Opteron 242 Opteron 244 Opteron 246 Memory Corsair Crucial Kingston Mushkin OCZ |
LOSTCIRCUITS |
SHORTCUTS:
The Multiplier Legacy Validating the New, Supporting the Old Apples to Apples and Clocks to Clocks System Disclosure, SiSoft Sandra Memory PCMark2002, A Different Perspective Benchmarks that won't: CodeCreatures, Comanche4 SPEC ViewPERF and diminishing returns Fraggin the Quake3 Arena Scores Expendable and the Chipset Frequency, 3DMark2001SE 3DMark2001SE: Behind the Looking Glass Profiling Performance, Will Barton Challenge Hammer? AMD Processor Steals |
| 333 MHz FSB for the Athlon The Unkept Promises | |
| (Review by MS, September 2, 2002) |
Test Configuration
|
|
SiSoft Sandra Memory Benchmark
By definition, raw Integer and Floating Point performance of a CPU does not change with manipulation of the front side bus as long as the clock speed is kept constant and in this case, we don't see any exception from the rule.
What will change though are the memory bandwidth numbers at the different settings, that is there will be some samll increase in bandwidth by going from the PC2100 speed to the PC2700 mode but, as outlined earlier, the difference will be small, courtesy of the limitation of the front side bus and the extremely high efficiency of the streaming and prefetching used for the buffering iteration of the benchmark.
As shown above, the impact of increasing the memory bus frequency only is minimal on streaming bandwidth. Rationally looked at, the results make perfectly sense in that streaming applications combined with prefetching or buffering can saturate the bus by staying in page for roughly 95% of all accesses. This can provide seamless back to back transactions because of the early issuing of a Read Command possible in DDR. On the other hand, it means that, if only one part of the two-tiered system bus bandwidth is increased, there won't be any benefits and that is exactly what happens here. Taking everything one step further, we are looking at an increase in FSB as well and, thus, the overall bandwidth available is 2.7 GB sec. A roughly 200 MB/s difference to the maximum possible bandwidth appears quite high but keep in mind that we are still working at over 92 % bus efficiency for the ALU bandwidth and a little less for the FPU bandwidth.
Overall, we are looking at a very impressive increase in available bandwidth but keep in mind that this will affect mostly streaming applications.
next page: => PCMark2002 =>
