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SHORTCUTS:
The Multiplier Legacy Validating the New, Supporting the Old Apples to Apples and Clocks to Clocks System Disclosure, SiSoft Sandra Memory PCMark2002, A Different Perspective Benchmarks that won't: CodeCreatures, Comanche4 SPEC ViewPERF and diminishing returns Fraggin the Quake3 Arena Scores Expendable and the Chipset Frequency, 3DMark2001SE 3DMark2001SE: Behind the Looking Glass Profiling Performance, Will Barton Challenge Hammer? AMD Processor Steals |
| 333 MHz FSB for the Athlon The Unkept Promises | |
| (Review by MS, September 2, 2002) |
Quake3 Arena
Outdated or not for testing graphics cards, everybody knows Quake3 Arena, everybody still loves the fragging action and every reviewer hates it by now but we won't let that come in the way of scrutinizing the effects of faster memory and/or FSB settings. Shall we?
"Fastest" 512 x 384 x 16 bpp
Again, we are getting a performance delta of 14% between the 133/133 and the 166/166 MHz setting. We know that Quake3 Arena is capable of using a substantial amount of prefetching, therefore, the total available bandwidth throughout the entire path from system memory to CPU will be more critical than increasing the bandwidth at the back-end of the path, that is memory bus alone. It is actually nice to see a system behaving according to the expectations, that is, the increase of the memory bus frequency alone only yields some 5.5% performance increase while the increase in FSB earns another 8% boost in frame rates.
"Normal" 640 x 480 x 16 bpp
Increasing the resolution to 640 and moving to more elaborate lighting and detail settings slightly compresses the scale to 5.2 and 7.4% relative increases, respectively for a total gain of 13% between the "pure" 133 and 166 MHz settings.
Bottom line is that the higher the optimization of the game engine towards prefetching, the lower will be the impact of increasing the memory bus frequency alone without increasing the FSB to overcome the bottleneck at the back-end of the path. To rephrase this, if the application is optimized for prefetching, it will run at very high bus utilization which means that at synchronous settings, the FSB and the memory bus will be at equilibrium and both buses will already be close to saturation. Increasing the memory bus alone will only result in "piling up" of data at the chipset level since the FSB is no longer capable of moving the data to the CPU. That is, unless the FSB is increased as well.
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