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With the release of the Athlon XP 1900+ AMD confirms its capability to deliver the next step in QuantiSpeed performance by announcing the 1900+ speed grade. Technically, the new CPU is identical to the earlier XP revisions with the exception of the CPU multiplier that has increased to 12x. As with all multiplier step-ups, latencies increase relative to CPU clock speed and this causes a minor performance lag behind the theoretical power, at least in bandwidth intensive applications. In FPU intensive applications, the increase in core frequency pays off in almost linear fashion. With respect to overclocking, the XP 1900+ reached some 12 MHz higher than the previously tested XP1800+. The small gain in highest stable clock speed may not be representative as the 1800+ in question appears to run exceptionally well and, moreover, there are reports of XP1900+ that potentially reach 1800 physical MHz.

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Upfront, this will be a short review because there is no new technology compared to what we described in the last reviews of the Athlon Palomino series. Essentially, what we are looking at is a new speedgrade which always raises the question whether a small step is really relevant to warrant a new review, particularly, since with the older XP1800+, we already exceeded by far the real clock speed of the Athlon 1900 XP+ running at 1600 MHz. On the other hand adding new speedgrades is a clear signal from AMD that introduction of the QuantiSpeed rating and the consequent higher rating was not a one time shot in the dark but that there is a commitment to keep on moving, refining the die and pushing the 2 GHz barrier sooner or later, either in QuantiSpeed MHz or real frequency, whichever comes first (not too hard to predict)

A brief synopsis of the technical specs

Compared to the original Thunderbird core, the Palomino increased the transistor count by 500k to 37.5 million transistors. New features are:

• the addition of the missing 52 SSE instructions to speed up integer operations through single instruction - multiple data (SIMD) algorithms.
• In addition, the Palomino core features a thermal diode to prevent death by frying. The thermal protection feature is not capable though of preventing burnout if there is no heatsink at all attached.
• The translation lookaside buffers (TLBs) have increased in size and efficiency to allow better caching of the virtual address space of multiple software applications running in parallel. Organic packaging (organic pin grid array; OPGA) is used as a cost saving feature with the additional advantage of a lower dielectic constant and higher resistance to reduce electrical crosstalk at high frequency.

With any new speed grade / faster CPU one needs to keep in mind that simply adding another few MHz over an existing design by changing the multiplier alone, system performance does not necessarily scale along with the expected speed bump. There are system bottlenecks that need to be addressed, foremost I/O latencies of the storage media but of no minor importance are the memory and front side bus latencies.

About 1 year ago we claimed that with the move towards DDR memory technology, the performance ceiling would be lifted from some 1.2 GHz to roughly 2 GHz and even though we are not quite there yet, there are indications that we start to see some impact of limited data availability on performance.

There is no mystery or prescience (not even female intuition), the facts are simply that a 12 x multiplier means that there are huge latencies alone in the initial memory access. For example, after a data request is issued, the CPU runs idle for 1 (command rate) + 2 (RAS-To-CAS delay) + 2 (CAS latency) = 5 bus cycles or 60 CPU cycles. Keep in mind that those are the waste cycles from the moment when the memory controller starts requesting the data. Before that, there are other latencies in the command sequence from the CPU to the controller (chipset) and with every step in the CPU multiplier, these latencies increase relative to the CPU power. In other words, in terms of the I/O interface, a 1600 MHz (12 x multiplier) looks exactly the same as a 1533 (11.5 x multiplier) CPU or any other, lower speed grade, but the amount of empty magnification, that is, power that cannot be used increases with every new speed grade.

Consequently, one can no longer expect that there is a linear increase with performance unless one looks at applications that are very good at utilizing single instructions to output multiple data. This operating scheme of SIMD, SSE, 3Dnow! is gaining tremendous momentum since otherwise, the CPU would just sit there idle. Superlong pipelines are another way of queuing data to the core but again, this doesn't necessarily increase performance either as evident from any RISC processor able to smoke the entire x86 community at half the clock speed.

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