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LOSTCIRCUITS

SHORTCUTS:
The Challenge
System Disclosure and Benchmark Results
Conclusion and Future Outlook
 Athlon XP2100+   
The end of the Palomino line
(Review by MS, March 26, 2002)
Conclusion

Granted that Content Creation Winstone2001 is somewhat specialized, it still reflects what has been touted as the future of the PC application, that is multitasking of heavily CPU and memory intensive applications. From the outcome of the benchmark runs, we come to several conclusions:

First and foremost: more system memory does buy better performance. In a somewhat obscure form, this was already posted on the Crucial website several months ago.

Second: the current 133 MHz bus with the synchronous DDR 266 interface is approaching its limitations as predicted some 18 months ago in this article on [H]ardOCP, since we don't see much performance increase by just another speed bump at the expense of internal latencies.


Third: Multitasking pushes the limits of what a standard Level2 cache can handle and even that is a Catch22 situation. The reason is that repetitive accesses of data from the L2 cache will lead to an expiration of the main memory page. With Hyperthreading, we predict that the situation will be even more complicated, leading to an even higher ratio of page misses. This, in turn, underscores again the importance of latency vs. bandwidth. With more complex applications entering the consumer space, we might as well be looking at the cat that bites its own tail. That is, in order to justify higher CPU performance, more complex applications have to be created which is nice since they offer more potential for creativity and the actual use of what makes a PC go beyond a calculator on steroids. On the downside, the very same applications that can make use of the higher power of the current and next generation CPUs will also require more data that need to come out of main memory (in the best of all cases) or else from mass storage media. In the latter case, even the current CPUs are an order of magnitude ahead of the storage media and, thus, additional speed grades will not matter unless the infrastructure of the entire system is changed.

This is where the I personally predict a great future for the AMD Hammer family with its integrated memory controller that, if our predictions are correct, will at least cut the chipset latencies to about 1/20 of the current lag. In addition we will need to see a revolution rather than an evolution of the storage media, serial ATA (II) will be one step in this direction, large disk caches combined with smart prediction algorithms will be needed just as badly.

Where does this leave the up and coming Throughbred and Barton families? First of all, not all applications are ContentCreation Winstones, there are games, office applications and most of all, there is a smaller die size and the consequently reduced production costs. To add, we have the reduced power requirements and SOI technology which needed to be shown as a feasible approach just as well. However, there can be very little doubt that, at least from a technological standpoint, the end of the K7 era is nearing. A logical step in the interim would be to move to a synchronous 166/333 or even 200/400 MHz FSB/DRAM interface, which could extend the life of the K7 platform. On the other hand, this would also require validation of the new bus speed. It might be something to fall back upon if everything else goes wrong, however, AMD's lack of effort in this direction and the possible cancellation of the Barton can only be interpreted that the Hammer family is moving very close to its public launch.

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