Massman wrote:First of all, I'm terribly sorry if this isn't the appropriate subforum for this question, so feel free to move it. Also, I have posted these 'questions', or musings if you will, already on my local forum boards, but the response is non-existant.
Excerpt from forum post:
"This (133x4=666MHz) is the memory running at highest possible frequency, at a stock BLCK frequency. But, that's not the most interesting part about this screenshot. Please have a look at the frequency of the uncore: 1995MHz. On a triple channel i7 platform, the minimum frequency of the uncore would've been 2660MHz, as in 2x the memory frequency (1330MHz DDR); on this dual channel platform, we see that the minimum uncore frequency is set at 1,5x the memory frequency. Why? I don't know. At least, not yet ...
After exchanging ideas with several more knowledgable people, it seems to me that the limitation of a minimum uncore frequency being twice the memory frequency is more of marketing purposes than really a technical limitation. To explain this, let's have a look at the AMD platform first, because it's also a dual channel DDR3 platform. AMD representatives acknowledge the fact that to really put the memory frequency to good use, you need a NB frequency of at least 3x (DDR -> 1,5x) the memory frequency. So, with an IMC frequency of 2GHz, you would only need a memory frequency of 667MHz (DDR3-1333). Anything higher would still scale but less and less intensively, at which you can ask yourself the question if you want to spend the extra money on high-rated memory kits. This 'theory' has been developped, tested and confirmed by Tony of OCZ, click for more information.
For Intel-based platforms, the story isn't that much different: the memory controller is now integrated in the processor and the clock frequency of it can form a bottleneck with high-frequency memory. The novelty about the i7 was the newly introduced third memory channel, which should increase the memory bandwidth significantly. Many tests, however, confirm that the extra channel doesn't have that much of an effect in most benchmarks, let alone in daily computing activities. And that is a big problem when trying to sell the product: who wants to pay more for something that doesn't work in the first place? The technique is quite simple: make it look like it works. And that's where the limitation of "uncore >= 2 x memory" kicks in: with an even lower uncore frequency, the added memory channel would have had even less effect than it has now. Less than almost insignificant, that's bad PR. Technically, it seems possible for the uncore to run at a lower ratio than 2:1, but weirdly enough none of the motherboard manufacturers seem to have added this option to their bios, although it would help people reaching 2000CL7 on air cooling since the memory overclock is very often limited by the uncore frequency."[/i]
(~ http://www.madshrimps.be/vbulletin/f10/ ... d80-65278/)
The question is in fact quite simple: am I being too critical or thinking too much in lines of conspiracy theories to believe that manipulating the Uncore frequency is just a marketing tool rather than battling with technical limitations? The LGA1156 platform shows me that it's perfectly possible to have an Uncore multiplier running lower than 2x the memory frequency and I'm quite reluctant to believe it's because of the missing third memory channel.
Also, it seems that the i5 7xx series only have memory ratios upto 2:10 (or 5x), whereas the i7 8xx series have ratios upto 2x12 (6x) ... to feed the 8 threads which are present on the 8xx, but not on the 7xx? In any case: for more multipliers, you need to pay more. Coincidence or marketing strategy?
In any case, if it's indeed just a marketing tool, and there's no technical limitation regarding Uncore/memory frequency, why has no motherboard manufacturer been trying to figure how to 'crack' the limitation? I mean: most of the performance enthousiasts are ignorant when it comes to finding the right balance between frequency and timings; 90% just applies the "more equals better"-rule and buys $350 2000CL7 memory kits only to find out their CPU isn't capable of running 4GHz uncore on air cooling. Having a motherboard that allows users to downclock the uncore would be a smart move marketing-wise.
M_S wrote:That one is easy- at least with a few assumptions. In triple channel mode, the uncore clock has to be twice that of the memory because in a triple channel configuration, the combined bit bus width meets the interface between the L3/uncore to the CPU that we assume to be at least 96 bit wide (1/2 of the 192 bit wide memory data path). In other words, every triple-channel memory transaction has to be split into two transactions between the uncore and the core, or else the L3 if it is used for prefetch. Only caveat is: we don't know the width of the uncore-core interface on the Core i7 (central queue) and I have not been able to find any conclusive data on this feature. However, if the uncore (or non-core in Intel's parlance) is interconnected with the core through the assumed 96 bit interface, then a 128 bit memory transaction will take at least 1.33 cycles to transfer. If you make the uncore clock 1.33 x of the memory then you use the entire possible bandwidth of all registers that are involved but you will end up with alignment issues in that the first transaction ends 1/3 into the register, the second one will have to start overlapping at 1/3 and end at 2/3 and so on, making things a bit complicated. Easier is to throw away a bit of frequency and use a 1.5 x clock where you have always full transactions with a boundary at 50% of the register width. You throw away a few bits but management is much easier that way.
Off all the different features on the architecture, that particular interface is one of the less likely items to be changed, whereas the memory controllers are just modular blocks that can be thrown in or deleted at lib.
M_S wrote:Different architectures and interconnect width will result in different requirements for the interaction of the different components. The AMD interconnect, for all I know, is totally different from the Intel architecture, there you have independent memory controllers, whereas, in Intel's approach all three controllers are always doing the same thing (even if the physical addresses may possibly vary.
KTE wrote:I'm predicting Intel will try to favor Core i7 sales as much as possible and if they think things aren't moving ahead fast enough, they'll play the Q6600 card. Mid-priced but increase its overclocking margins to near the higher-end models so it becomes a hit.
KTE wrote:If they're moving Uncore to the IGP die in Westmere, does that mean all the major components currently situated in the Uncore (like the PLLs, MCs, L3 and PCU) are also being moved?
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