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Back to the ATA/ATAPI standards: The numerical suffix designates the highest transfer rates that the interface can sustain. In the case of UATA-133, this would be 133 MB/sec, which is also the limitation of the PCI bus at the back-end of most ATA controllers. Therefore, it is not possible to increase transfer speed or add faster standards within the framework of the existing PCI specifications. Also keep in mind that the strobe frequency, which determines the transfer rate is negotiated between the controller and the device upon initialization using a handshake protocol and, therefore, a UATA-66 drive will still run in UATA-66 mode even when it is connected to a UATA-133 controller. One other important issue to keep in mind is that the real time transfer mode of DOS and 16-bit Windows was abandoned with the move to Windows 95b, likewise Unix and Linux are using Protected Mode, which means internal scheduling of transfers on the level of the OS. This is important in that the OS can determine the most economic way of getting the data in and out from the host bus adapter (HBA) to the drive and back.

In theory, if everything else works out, it should therefore be possible to achieve 133 MB/s data transfer on a UATA 133 controller. However, data are not the only thing that are transmitted across the cabling / controller. The data (ribbon or SATA) cables are shared between data, addresses and commands. This means that either data or commands can be communicated at any given time. The term "commands" actually does poor justice to the string or framework of information that is communicated, therefore, the aggregate command-address information structure is using a different terminology called "frame information structure" or FIS. Any FIS contains all necessary instructions about the data that are about to be accessed or the commands that are about to be executed.

The easiest way to explain this is probably to draw a comparison to either system memory or AGP transfers. System memory uses three separate buses or sets of lines, that is, the command lines, the address lines and the data lines, which means that either set of "data" can be propagated independent of the other. AGP used to have a shared interface, however, with the introduction of sideband addressing (now mandatory in the AGP 3.0 specs) the address and data buses were physically separated. With HDDs, the problem is that the cable distance is too long to add all the extra lines without running into a whole new ballpark of problems, therefore, the shared bus is still the best way to go.

Comparison between different "data and instruction" configurations. The top schematics are representative of e.g. system memory and AGP 3.0. After the command is issued, it takes a certain access latency (grey) until the data are output (gunmetal) however, since the data and command buses are not shared, it is possible to do almost seamless back-to-back transactions. This protocol can further be optimized by issuing the commands a bit earlier to avoid the "starting over" access latencies. HDDs are using a shared data and CMD bus which means that data are alternating with commands or FIS' (middle schematics). However, intelligent drives are using the command phase to execute look-ahead or read-ahead (blue) algorithms for internal data prefetching into the drive cache, meaning that as soon as a command is issued, the data can be burst onto the bus without any further latencies (lower schematics).

next page:    => Hard Disc Drive Architecture III: Quantifying the FIS Overhead =>