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PCI Latency

Other factors contribute to the overall efficiency of the host transfer rate. Among those factors are PCI latency, as well as bus parking algorithms on the interrupt request line (IRQ) of the system. Briefly, PCI latency refers to the number of cycles that any device can hold an IRQ before it is disconnected as a function of fairness algorithms. The average access latency varies from one system to another but a good example is 8 cycles. This means that if the latency is set to 32 cycles, the ratio between access latency and transfer cycles will be 1:3. Increasing the PCI latency to e.g. 64 cycles will change this ratio to 1:7 (since the access latency remains unchanged) and this will allow more data to be transferred on each access and also reduce the relative access latency overhead. Most burst rate testing protocols are using transfers that are in the order of 2-8 KBytes, which means that, with a 4 Byte wide bus, it will take 512 - 2048 cycles to complete the transfer, after which the average speed is calculated from the amount of data and the duration of the transfer.

Bus Parking

If the PCI latency is set to e.g. 64 bus cycles, it will still take 32 iterations of the same 64 cycles with disconnect from the interrupt request line and reconnect after the access latencies are met each time, to push the 8KB test data through the PCI bus. This means that there is a fair amount of cycles that are unnecessarily wasted. The termination of the access after a given maximum latency, however, is necessary because fairness algorithms need to be implemented in order to avoid starvation of other PCI devices by one or two resource hogs. However, the PCI specifications also provide the "best of all world" scenario by allowing a bus parking scheme. What that means in layman terms is that the device will grant access to other devices of the PCI bus if such request are being queued. However, in case there are no outstanding requests, the bus master will stay parked on the IRQ without relinquishing it completely and, if no other device grabs the bus, it will continue with data transfers in back to back mode.

We used an arbitrary access latency (no transfers) of 8 cycles to illustrate the impact of the PCI latency on the overal PCI bus bandwidth. In case the latency is set to 16 cycles, the sustanined transfer rate drops to 67 MB/sec since 1/2 of the cycles is wasted for access latencies after the bus has been reliquished, 24 cycles will result in 89 MBs, 32 cycles in 100 MBs, 48 cycles in 111 MBs and 96 cycles in 121 MBs. If bus parking is supported by the PCI arbiter, the latency does not matter that much anymore since the strobe will "park" on the interrupt until another device gets priority. Keep in mind that the IDE controllers are using IRQs 14 and 15, which are the highest priority interrupts.

Write Combining

There are additional mechanisms like PCI write combining and/or delayed transactions, which are basically doing the same thing, that is, combining data within special "write combine buffers" and then transferring them using a burst protocol to ensure most efficient transfers with the lowest bus "occupation".

In some older systems, write combining may not work, depending on the overall configuration of the system. For example, some PCI graphics cards do not tolerate write combining, a classic example is the Voodoo 5 PCI version. The drawback is that everything else on the PCI bus, that is, network controllers etc will start stuttering. Similar issues are found with some of the Soundblaster Series sound cards on VIA chipsets.

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