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IN THE PREVIOUS ARTICLES we have concentrated on some of the internal design parameters that influence the internal performance of Hard Disc Drives as well as some of the issues that relate to the effective host transfer rate and the interfacing of the drive with the Host Bus Adapter (HBA) and the DMA and busmastering channels needed to interface with the system logic. The current article will concentrate more on the differences between Parallel and Serial ATA with a focus on the different interfacing protocols

Most of the marketing strategies promoting the migration from Parallel to Serial ATA have focused on the physical cabling properties, that is, the reduction from 16 bidirectional data channels to two unidirectional pairs of Low Voltage Differential Signaling ((LVDS) lines. On the surface, the obvious effect is a greatly facilitated ease of routing, reduced obstacles in the air flow and a smaller connector footprint. The main reasons, however, relate to the signaling properties in the context of the fact that parallel signaling across long distances had no headroom left for further speed grades.

Cabling and Parallel Signaling Properties

The most compelling reason for the move to Serial ATA has been the preservation of signal integrity along the cable. Briefly, Parallel ATA has been pushing the limitations of any ribbon cable design, in that the original 40 wire ribbon cables were already long enough to allow jumping of signals across the data lines at high signaling frequency - a phenomenon also known as electrical crosstalk. After the addition of interleaved shield wires, which brought the total wire count up to 80 wires, this cross-talk was largely eliminated, however, the reduced diameter of each wire caused the next problem in the form of uneven signal propagation. As a result, signal delays occurred across the sixteen data lines, meaning that in some lines, the data will arrive at the connector earlier than in others, a phenomenon known as signal skew. The problem with signal skew is that it reduces the so-called "Data-I", that is the window during which all bits are valid as either logical true or false. Other terms for Data-I are Data Valid Window or tDV.

Timing diagram for Parallel ATA showing the switching time after subtraction of setup and hold time from the hemi-cycle in an ATA-100 configuration.

If there are delays in some of the wires, the actual data window in which all data across the bus are valid can be shortened dramatically. The drawing is exaggerated to illustrate the problem.

This leads into the next set of problem, namely the reduced data window or switching time across the parallel pathway. This data window is defined as a hemi cycle time (since a DDR protocol is used) at any given frequency minus the setup and hold times. Suffice it to say that UATA-133 or ATA-ATAPI 7 has reached the ceiling of what a parallel cable using current manufacturing standards can carry.

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