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As already mentioned above, Serial ATA uses only a single channel for each upstream and downstream signaling. Instead of using a conventional low - high (3.3V) voltage swing as measured against a "fixed" ground, each LVDS channel utilizes a pair of wires where the voltage differential between the two lines becomes the actual signal. In other words, at e.g. 400 mV amplitude of the voltage difference between the two lines, anything lower than 200 mV would be a 0, everything above 200 mV would be a 1.

Because of the low voltage swing, LVDS technology transfer frequencies (depending on the length and the diameter of the wires) can be pushed up to 10 GHz data rate. In the context of a 10 bit/Byte conversion, this translates into a data bandwidth of up to 1 GigaByte/second.

Current SATA technology is still a far cry from this bandwidth. The present signaling technology goes up to 1.5 Gbit/sec for 150 MB/sec bandwidth. However, in contrast to the Parallel solutions, limitations are no longer posed by the cabling and connectors but are found mostly on the level of the controllers and the downstream connection to the core logic or host bus.

Shared Bus Issues

ATA, regardless of whether it is Parallel or Serial technology, uses a shared bus, that is, the same "data" lines for the issuing of commands and the transfers of data. Commands and addresses for the data are issued in the form of so-called Frame Information Structures (FIS) with a typical size of 8 kB. We already mentioned [http://www.lostcircuits.com/hdd/hdd4/] here that the FIS' constitute a sizeable command overhead, depending on the size of data transfers requested by the controller. In Parallel ATA, this command overhead already exists on the level of the ribbon cable since those cables can only carry one signal at the time.

Parallel vs. Serial cabling and I/O configuration. In Parallel ATA, sixteen individual data lines connect the HBA to the drive in a bidirectional functionality. In SATA, two pairs of Input and Output lines provide one single high speed channel for each Input and Output.

In contrast, in SATA technology, the separation of input and output lines will allow, at least in theory, a simultaneous propagation of commands through one pair of LVDS lines and READs through the second pair. This is called a full-duplex mode with the benefit that the commands no longer interrupt the data transfers, which can now be spliced together for a seamless stream in back-to-back mode. Keep in mind that this will only be necessary or possible for data that are burst out of the cache. Media or sequential transfers will be slow enough to free up the bus in between transfers anyway.

Also keep in mind that simultaneous READs and WRITEs are not possible unless a physically separate read and write cache is implemented since DRAM technology only allows either read or writes signaled to the chip by pulling the Write Enable pin high (logical false) for READ or low (logical true) for WRITEs. Simultaneous READ and WRITE transactions would require separate memory chips on the drives and separate controllers. Because of the already existing performance bottleneck on the level of the platter or media, there is no need for implementing this level of sophistication.

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