The two major buzzwords of the i7 architecture, developed under the codeword “Nehalem” are the triple-channel integrated memory controllers and the new interface called Quick Path Interconnect or short QPI. Additional highlights encompass the monolithic die to consolidate all four cores in a single piece of silicon, and the shared L3 cache. Further tweaks include power management, streamlined data pipelines and improved TLBs as well as load-dependent overclocking and we’ll cover each item in more detail below.

Quick Path Interconnect

We mentioned that the main crux of Intel’s FSB was the bidirectional nature of the bus, meaning that data could only move in one direction at any time. The bus congestion was partially ameliorated by adding clocks and in the final version, the FSB was operating in quad-pumped mode, meaning that on each clock a total of four bits were transferred on each data line. At 400 MHz nominal frequency, this results in 1600 MT per clock or potentially 12.8 GB/sec – but only one way at any given time.

In this respect, the Alpha and later AMD HyperTransport technology has been a much more elegant solution for years now, using a much narrower full duplex bus and compensating for the lack of width by using much higher frequencies. On a technical side, the FSB with its one-line – one bit protocol with its reference voltage to determine I vs. O could not scale much higher that 400 MHz, at least not for qualified mass production. The way around this type of limitation is to resort to low voltage differential signaling, meaning that two traces constitute a single lane and the signal is decoded from the differential in voltage between them.

Functional overview of Intel's Quick Path Interconnect

In the case of the i7 QPI, Intel is using a total of 21 lanes in each direction (1 clock forwarding + 20 data lanes) using two traces each for a total of 84 traces that also carry commands and addresses in packetized transfers. Overall, the result is a net saving in traces compared to the FSB where data command and address buses were separate from each other.

Depending on the processor model, QPI may run at either 6.4 Gbps or else 4.8 Gbps to achieve 12.8 or 9.6 GB/sec bandwidth to communicate with the X58 Express chipset in each direction. In marketeering parlance, this is a 25.6 GB/s interface but to give credit where credit is due, the bus supports simultaneous transfers in both directions and therefore using the full duplex bandwidth is not illegitimate.

QPI power states illustrated

In future generations, QPI can also be used to cross-connect multiple processors in any multi CPU configuration but we are not quite there yet and will cover the technology once it becomes available. On a short note, the QPI bus allows multiple power states from L0 to L0s and also features self-healing capabilities in that bad lanes can be turned off to keep the system running, albeit at a minor performance degradation.