Measuring Isolated CPU Power

This leads to the next question, namely, how to actually measure the combined power: This is where things are getting complicated. Essentially all processors to date receive their core supply voltage from the auxiliary 12V lines that have been increased to four 12V input lines of 5A max current each for a combined maximum power of 240W. Arguably, the cores including cache are the biggest single factor contributing to the total power consumption of a processor.

However, as mentioned earlier, even in classic CPUs (using an external memory controller as part of the NorthBridge), other factors contribute to the overall power picture, primarily the bus interface, being powered by a shared power plane between the system core logic and the CPU. In the case of AMD’s processors, this would be the Hypertransport voltage (VHT), in the case of Intel’s CPUs (up until the Core i7) it is the AGTL or FSB voltage. Both of them are derived directly from the motherboard input voltages, depending on the design either from the 3.3V or the 5V rail coming in through the 20- or 24-pin ATX or EPS connector. Even if it was possible to measure the power output directly at the dedicated voltage regulator module, one would need to keep in mind that the power is shared between at least two ICs connected over the bus and in so far it is essentially impossible to get precise measurements - at least using conventional test equipment.

Adding VDDQ to the CPU Power

With AMD’s Athlon64 line of CPU, things became even more complex in that the memory controller was moved to the processor. This means that another interface was added with its own power bus – again shared between the CPU and the “peripheral” in this case, the memory. More specifically, the “digital portion” of the memory controller, that is the logic remains powered by the actual “core voltage” but the I/O interface is powered through the memory I/O voltage plane: VDDQ. In general, the memory VDDQ power plane is not a huge contributor to the overall power profile of a CPU, most of the power is actually drawn during writes to the memory, but it is a factor nonetheless regardless of how big or small it may actually be in reality.

Suffice it to remind of the sensors present in some of Intel’s Memory Controller Hubs that were monitoring overall current draw during writes and that also were inserting mandatory wait states in cases where the write currents exceeded the chipset limitations. However, this also needs to be viewed in light of the fact that the NB heat-sinks are generally more of the flimsy kind, something that would be able to cool a VIA C3 processor, in other words, we are talking about 10W or less including the actual address translation. Given the somewhat sporadic nature of memory writes compared to reads it is hard to put an actual number on the power consumption of the I/O section but we would estimate something in the order of 3-5W under load judging from various specifications.

AMD’s Phenom : Adding the NorthBridge to the CPU

AMD’s Phenom was the first CPU to officially use the term NorthBridge in the description of discreet parts of its logic (even though the term was casually introduced with K8 tools and K8 BIOSes as NB/IMC). In the K10, the NB power circuitry was uncoupled from the actual core PLL and power supply to allow separate power and frequency gating of the CPU cores on the one side and the NB including the shared L3 cache on the other side. Depending on the motherboard, the core logic and voltage regulator modules used, the Phenom processors could be run either on split voltage power planes or, in case of older motherboards retroactively adapted to accommodate Phenom via BIOS updates, they might just run on a common power plane. One thing important to consider here is that even though there is a split voltage option and power separation between the core and the NB, the power input is still derived from the discreet 12V auxiliary power input without drawing additional power from other rails. This is important because the large L3 cache is a prominent factor in the overall power scheme, likewise, the digital portion of the memory controller also supplied through these rails cannot be neglected with respect to power, even if the I/O power is derived from the memory VDDQ plane.

Clock Domains

In the case of the Athlon64 series, the memory clock was derived directly from the CPU core frequency by means of a divider, leading to all kinds of odd memory frequencies. With the Phenom, AMD uncoupled the memory controller from the actual core frequency; depending on the model, Barcelonas and Phenoms are running their NB including the shared L3 cache at 1400-2000 MHz, and the memory frequency itself is configurable to the standard frequencies of 400 – 1066 MHz (DDR2)