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AM3: A new Socket for DDR3 support
Socket AM2 and AM2+ have 940 pins and support DDR2 exclusively. However, with the release of Phenom II, AMD has finally added official support for DDR3 on the platform level (supposedly, though, all Phenom DCs unofficially already supported it). In a case like this, the actual differentiator is the de facto validation of the new technology which has been entirely missing from the Agena core since, in a nutshell, there were enough other issues to be dealt with.
The new line of AM3 processors needs to be fully backwards compatible with the existing DDR2 technology, yet, for legal reasons, the older “non-validated” processors have to be excluded from out of the box use with AM3 platforms and DDR3. Accordingly, the form factor needed to be changed in a manner that allows the AM3 CPUs to seamlessly integrate into the AM2 platform while at the same time prohibiting the insertion of an AM2 CPU into a DDR3 platform. To accomplish this, AMD resolved to the oldest trick in the book to solve the problem by removing two pins from an otherwise unchanged pin-configuration. As a result, the AM3 CPUs sport 938 pins instead of 940, which allows them to plug into the AM2 sockets - missing pins have never been in the way of insertion. Socket AM2 CPUs with 940 pins, however, will not fit into the 938 pin-out of the AM3 platform.
At deadline of this article, we weren’t able to secure any AM3 – DDR3 motherboards for extensive testing, however, we will follow up as soon as availability of hardware permits.
AMD Phenom II X4 810 and X3 720 Processor Specifications
Socket AM2(+) and AM3 side by side: Note the two missing pins in the "key" areas of the pin array (circled).
| Processor Frequency: | X4 810 = 2.6GHz / X3 720 = 2.8GHz |
| L1 Cache Sizes: | X4 800 Series: 64K of L1 instruction and 64K of L1 data cache per core (512KB total L1 per processor)
X3 700 Series: 64K of L1 instruction and 64K of L1 data cache per core (384KB total L1 per processor) |
| L2 Cache Sizes: | X4 800 Series: 512KB of L2 data cache per core (2MB total L2 per processor)
X3 700 Series: 512KB of L2 data cache per core (1.5MB total L2 per processor)
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| L3 Cache Size: | X4 800 Series: 4MB (shared)
X3 700 Series: 6MB (shared) |
| Memory Controller Type: | Integrated 128-bit wide memory controller * |
| Memory Controller Speed: | Up to 2.0GHz with Dual Dynamic Power Management |
| Types of Memory Supported: | Support for unregistered DIMMs up to PC2 8500 (DDR2-1066MHz)/ PC3 10666 (DDR3-1333**) |
| Theoretical Memory Bandwidth: | Up to 21GB/s |
| HyperTransport 3.0 Link: | One 16-bit/16-bit link @ up to 4.0GHz full duplex (2.0GHz x2) |
| HyperTransport 3.0 Bandwidth: | Up to 14.4GB/s |
| Total Processor Bandwidth: | Up to 33GB/s total bandwidth |
| Packaging: | Socket AM3 938-pin organic micro pin grid array (micro-PGA) |
| Fab location: | Fab 36 wafer fabrication facilities in Dresden, Germany |
| Process Technology: | 45-nanometer DSL SOI (silicon-on-insulator) technology |
| Approximate Transistor count: | ~ 758 million (45nm) |
| Approximate Die Size: | 258 mm2 (45nm) |
| Max Ambient Case Temp: | 71/73° Celsius (X4/X3) |
| Nominal Voltage: | 0.875 - 1.425 Volts |
| Max TDP: | 95 Watt (all AM3 CPUs) |
*NOTE: MC configurable for dual 64-bit channels for simultaneous read/writes
**NOTE: At DDR3 10666 (1333 MHz) only one DIMM per channel is supported.
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