The Evolution of SMP and Multichannel Memory

Dual channel memory has been around since nVidia and Intel introduced it with their nForce2 and Granite Bay platforms, respectively. In case of Intel’s architecture, the term “dual channel” used to be a misnomer as we all know since the duality only circumscribed the combination of two 64-bit channels to one 128-bit Überchannel with shared address and command signals. In other words, the two channels were tied together and could only be accessed in unison to achieve 128-bit transfers instead of 64 bits per clock. In the case of the Core i7 Nehalem architecture, Intel has changed the strategy to have three independent controllers for three concurrent transfers of 64-bit width for a combined 196 bits per transfer. The same operational principle applies to the Core i5.

Dual channel in the above described form was originally developed to increase memory bandwidth as a complementary measure for increased clock speed of the Pentium4 line of CPU. However, at the time it was difficult if not impossible to demonstrate any tangible benefit, in fact, a number of lower cost chipset solutions were very successfully competing with dual channel arrangements. The lack of performance benefit, though, needs to be put in the context of the at the time prevaling system architecture, that is, a single core processor was the common CPU in use in most systems. Simultaneously with the introduction of the dual memory channel architecture by Intel, another technology, namely HyperThreading, emerged.

HyperThreading or HT, is based on the duplication of the architectural state, that is, the part of the CPU, which holds the state of a process and comprises control registers such as instruction flag registers, interrupt mask registers, memory management unit registers and status registers, as well as general purpose registers including adder, address, counter, index, stack and string registers. In other words, the architectural state serves as interface between the system, including memory, and the execution cores to schedule the workload in the most efficient way.

It is probably easiest to look at the architectural state as the part of the processor that is "visible" to the operating system. Consequently, duplicating the architectural state allows a single processor to appear as two CPUs, as long as the operating system supports symmetric multiprocessing, and to use the additional registers for streamlining multiple threads for execution.

To summarize the above, HyperThreading, allows the splitting of one single physical core into two logical cores, each of which can process its own thread. The latter of course stops at the execution units but either way one looks at it, there are some benefits, at least in some applications. What is important. though, is the convergence of dual channel memory with the dual processor cores, in short: two cores, two memory channels. As explained above, neither one is really the case in the scenario outlined, which, however, still serves as a good example to explain the trend we will be redlining in this article.