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AMD "Llano" A8-3850 Print E-mail
Written by Michael Schuette   
Jul 05, 2011 at 02:53 PM


As much as we liked AMD’s C and E-series Ontario and Zacate APUs, there was never a doubt that they were really entry-level processors with attached graphics that were a bit ahead of the CPU. Even the graphics, though, were limited by the somewhat anemic memory interface. That is, a single memory channel running DDR3-1333 at the most and shared between two cores and the GPUs is crying starvation for every component. Even if the memory channel has a theoretical bandwidth of 10.6 GB/sec, practice will rather yield some 50% of that value only, which is then shared between CPU cores and GPUs. For the moment, we’ll leave it at this as a simple stepping stone on the way to “Stars” or Llano that brings the long overdue A-series of APU to market.



In a nutshell, the Llano APU is AMD’s first processor manufactured at the new Global Foundries 32 nm SOI-HK-DSL process. This comes at a time where Intel is already vying the next 2x node with folded or 3D transistors but for the moment, at least production-wise, there is parity once again in foundries land. With respect to the architecture there is hardly much new and revolutionary, the recipe is in fact rather simple, take the existing Phenom II cores, strip off the L3 cache and instead increase the existing L2 cache from 512 kB to 1 MB and add two instances of the Cypress-based “Redwood” GPU, now called Sumo. Then shrink the entire thing down to the new process. That does not sound too complicated and to really round things up, let’s add the latest generation of universal video decoder (UVD).

Let's quickly reiterate the individual steps starting with the concept:



The cores are only minimally altered by increasing the number of schedulers for integer and FP whereas the size of the L2 cache is doubled:



Take an existing graphics core and add it to the modified processor to tie directly into the NorthBridge and memory controllers.



Finally, add the universal video decoder:



Truth is, though, that the concept makes for maybe 5% of the work whereas the actual hooking up of all nodes and the tweaking, not to mention the difficulties that always arise with a new process amount to the remaining 95% of getting the entire thing to the point where it passes simulation and/or actually having working silicon. After that, there are still some minor hurdles to pass with respect to adapting the infrastructure to do justice to the word Fusion.



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Last Updated ( Oct 11, 2011 at 02:58 PM )
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