L O S T C I R C U I T S

When Intel first introduced the tick-tock slogan, I couldn’t help thinking it sounded a bit like something from a Stephen King book – or maybe it was The Shining... and, whatever it was, it didn’t sound too appealing. But that was only the name, whereas the concept rang true from the very beginning. In short, the best way to bring new generations of CPU out into the market is to leverage existing and proven process nodes for new designs and, once all the bugs have been fixed and errata have been documented, move on to the next process node with only minor modifications and additional features that are “playing it safe”. Now of course, the obvious question is what came first? The chicken or the egg but and depending on whether you talk to Mark Bohr’s group who is in charge of the process nodes or some of the CPU designers, the answer will be different. Most of us will probably agree that the new design comes first and therefore that one should be the Tick whereas the new process would be the tock. And that’s where we are wrong because everybody can design a CPU but how many of us can successfully give birth to a new process node? But I digress…

So here we are, it’s been a little over one year since the release of Intel’s Sandy Bridge processor (Tock) at the 32nm process node and Sandy Bridge has established itself as probably the best all around CPU in the desktop and mobile market. The main criticism has been that, even though a significant step up from Clarkdale, the graphics are still a bit anemic, with some major weaknesses especially in OpenGL performance but on the other hand, especially given the increasing dominance of smart-phones in the world of consumer electronics, Intel’s Quick Sync technology, powered by the media accelerators has hit a sweet spot.

Logically, the next Tick is going to be an improvement of the already successful features, along with maximizing the returns from the migration to the 22 nm process node, that is, better energy efficiency and adding some more graphics execution units at least to the flagship models of the new CPU without increasing die size. Another improvement for media processing comes from adding a second texture sampler/media sampler. Better efficiency in graphics processing is also achieved by adding a GPU-specific L3 cache on die to reduce access of the LLC via the ring bus. Finally and most importantly, the HD4000/2500 graphics (depending on the number of execution units) add support for Microsoft DX11.

Other changes are more on the CPU side, most importantly, single-threaded performance is improved by dynamically sharing data structures between threads via the decode streaming buffer (DSB) queue wherein decoded uops are stored for reuse and thus enhance performance for loops. In a very simplified view, this means that the CPU can, load dependent, dynamically switch between HyperThreading “On” and “Off” state, by allocating all buffer resources to a single thread if that’s the only one queued up. There are some other changes from SandyBridge like the FP/Integer divider and the power-gated DDR3 interface with support for low power DDR3 (DDR3L) and support for memory data rates up to 2800 Mbps and so on but none of these changes are real game changers.

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