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AMD Regor and Callisto, the New X2s Print E-mail
Written by Michael Schuette   
May 29, 2009 at 09:25 PM

It is always refreshing to see some new hardware coming out. Needless to say that the more exciting stuff always concerns the high-end solutions but not everybody is in the market for this kind of toy. From a financial standpoint, the low end has always been the "bread and butter" for any company and who doesn’t believe it just needs to check Intel’s latest statements regarding their Atom sales.

In the last months, AMD has gained substantial market share. Some of it has been offset by the slumping Opteron sales but the net effect is still an increase in market share. With the current CPU architecture, there is very little chance to compete against Intel’s Core i7 but again, if Intel has Nehalem and Atom as their key players, that leaves the door wide open for everything else in between. After the original Phenom, which was arguably a dud, Phenom II has picked up performance and, especially in the AM3 flavor, has reached parity or has outpaced most of the Core2 processors, at least on a $ for $ basis.

Phenom II, though, is costly to manufacture; 758 million transistors, even if they are crammed into 258 mm2, still take up 258 mm2 which translates in a limited number of die per wafer. In order to remain price-competitive especially in the lower market segment, AMD needs a smaller die with high performance and the latter is something that the original Athlon X2 can no longer deliver, not even with migrating the design to a 45 nm process. On the other hand, all current IC designs, including Phenom (II) are fairly modular, with the individual building blocks comprising the cores, the NB/IMC and the system request interface (SRI). In a nutshell, the recipe in this case was to take two cores and tie them to the dual channel NB/IMC after stripping out the 6 MB L3 cache. On the HT side, the known-good SRI didn’t need any replacement, therefore, everything stayed as usual.

Net savings of this operation come out to ~ 574 million transistors and ~ 158 mm2 resulting in a ~100 mm2 die featuring 184 million transistors. However, to make up for the lack of the L3 cache, AMD reintroduced the full size 1MB L2 cache last seen in the Clawhammer design. The result is a reduction by 524 million transistors and 141 mm2 for a final die size of 117 mm2 die and 234 million transistors. As for the name, there is neither need nor point in changing the brand awareness, a simple moniker addition suffices to create the Athlon II in its debut speed grade of 3.0 GHz, and dual core configuration. Enter the Athlon II X2 250, internal code name "Regor".

Allegedly, the biggest performance boost of Intel’s Core2 design was achieved with the shared L2 cache since both cores can directly access it without having to write back to system memory before loading the private cache of each core. AMD’s Phenom series has addressed this problem by using the shared L3 cache and in theory, all X2 processors have a crossbar switch to allow inter-core communication. In practice, however, the cross-talk between cores and L2 caches was never enabled and it does not appear to have happened with the new design either. In multithreaded applications, this can be a disadvantage since cache coherency needs to be managed on the level of the system memory. With the old system architecture featuring the memory controller in a separate north bridge on the motherboard, this would put any multicore CPU at a severe disadvantage. However, at least in a dual core situation, the integrated memory controller should allow AMD to treat the lack of cross-bar functionality as a relatively minor inconvenience only, compared to enabling the crossbar, which could result in a major hot-spot on the die and definitely kill some of the frequency head-room.

Of course, there is the "other" solution introduced with the "Heka" core – by itself a misnomer unless somebody can justify disabling a core as a new model code – and which is taken to the next level, code name "Callisto" by disabling two cores. Otherwise the processor is de facto a Deneb, featuring the same 512 kB L2 , and shared 6 MB L3 cache. At introduction, the new kid on the block is running 3.1 GHz, based off a 15.5x default multiplier. However, in order to increase the appeal of the Phenom II X2 550, it is released as Black Edition, meaning it is unlocked both with respect to core multiplier and, more importantly, also with respect to the NB frequency, a prerogative for taking advantage of DDR3 1600 with or without AOD’s latest BEMP feature.

Last Updated ( Jul 17, 2009 at 02:22 AM )
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