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Brave New World of SSDs: Part II Print E-mail
Written by Michael Schuette   
Nov 27, 2009 at 11:00 PM

Something Old, Something New ..

In the first installment of this series, I covered some of the peculiarities of NAND flash, especially in view of the unidirectional programming and the resulting problematic for solid state drives. To put things into perspective, flash memory was originally developed as an inexpensive media for digital cameras with rather limited write/erase cycles and, with the exception of some high-end cameras in use by professional photographers, rather infrequent accesses to the media.

It is fairly easy to appreciate how the adaptation of this low-cycle frequency flash technology into a completely different set of application, specifically the use in solid state drives can cause some problems. Moreover, adaptation of the ATA technology and related file systems to accommodate NAND flash also had to take a few hurdles to get where it is at the moment and, to be true, at the present time the coalescence of the two worlds still needs to be considered to be in its infancy, with the real thing yet to come anytime in the near or far future.

The easy way to accomplish a functional solid state drive is to take an ATA controller and strip it off the servo controller and the mechanical back end including actuator, heads and platters and substitute a flash interface typically consisting of an abstraction layer including the control logic. The abstraction layer translates logical block addresses (LBAs) into physical sector addresses using a similar virtual memory space as that used in main system memory. That is, there is no real correlation between the physical locality of two adjacent logical blocks, they can be physically anywhere within the array.

From HDD to SSD: Serial Transfers vs. Parallelization

Hard disc drives using rotatable media are strictly serial devices. Notwithstanding the number of platters, only one head can be active at the time for either read or write. Likewise, regardless of how complex the data structure is, there is no parallelism, unless several physical drives are combined in a RAID array. This changes completely in the case of solid state drives. The typical controller nowadays uses eight to ten channels to interface with the NAND flash chips and each channel is typically 8 bit (1 Byte) wide. Functionally, this has a number of consequences, especially for performance. In HDDs, the surface velocity of any given sector and the data density of the media define the media transfer rate, which varies as a stepping function, resulting in "zones" from the outer diameter to the inner diameter of the platter.

In SSDs, the bus frequency, including the clock at which the NAND flash chips are running, poses the theoretical limitation for the media transfer rate. Typical frequencies in the current environment are in the 50-60 MHz range using a single data rate protocol. With an 8 bit I/O width, each channel is therefore capable of transferring 50-60 MB/sec maximum peak bandwidth. Needless to say that this number is somewhat hypothetical since there is no such thing as 100% bus utilization in real life. Still, this number allows for a reasonably good approximation of what the back-end of a NAND flash interface is capable of. Based on 50 MHz, in a four channel configuration, the theoretical limit is 200 MB/sec, in an eight channel configuration, the limit is consequently 400 MB/sec. These numbers are currently changing with the transition of NAND flash to Toggle Mode flash using a DDR protocol and a slightly higher frequency of 66 MHz clock rate and 133 Mbps data rate. In a typical read application, this will increase the theoretical peak transfer by approximately 125%. Write performance is also increased, yet only by approximately 50%.

By now, this fact is somewhat trivial, but for reasons of completeness, I mention it again. In SSDs, there is no stepping function of media transfer rate depending on the track location as it is in HDDs where the OD tracks have noticeably higher transfer rates than the ID tracks. In SSDs all chips and all blocks are being treated equally, however, there are other limitations.

Last Updated ( Jan 03, 2010 at 04:41 PM )
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