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Brave New World of SSDs Part III Print E-mail
Written by Michael Schuette   
Jul 26, 2010 at 01:59 AM


Solid state drives are becoming increasingly popular. The trend started with the enthusiast and early adapter community, and arguably, there were a few bumps and glitches. Some of the primary issues were simply caused by trying to squeeze solid state drives into an environment custom tailored towards hard disk drives, some other issues were insufficiencies on the SSD controller, particularly with respect to the exact workings of NAND flash.

In several earlier articles, we already covered some of the important aspects of flash memory cells and the inherent limitations caused by "Fowler-Nordheim" quantum-mechanical tunneling as programming and erase mechanisms. We also covered some of the system-level challenges faced by SSDs along with countermeasures implemented in the latest versions of operating systems or drivers to keep SSDs at a steady state of performance by proactively performing TRIM and garbage collection.

The one thing we have not covered yet is the heart and soul of NAND flash memory, that is, the organization of NAND flash, as opposed to for example NOR flash or any similar non-volatile memory, which is the reason for its cost effectiveness but also has some functional consequences in the form of read disturb and write disturb. Disturbing? On the surface, yes, but not if you drill down below the surface of the buzzwords to understand what you are actually talking about.

The Flash Cell: a Floating Gate Transistor

As a short recap, flash memory cells are floating gate transistors (FGT). The principle of operation is that in addition to the control gate, flash memory uses a second gate positioned between the channel and the control gate, which is electrically floating and can absorb and release electrons from and to the substrate by passing them through an insulating oxide layer. The electron charge present in the floating gate either amplifies or else counteracts the control voltage level applied to the control gate to turn On the gate, that is, to make it conductive. That is, the less negative charge is present in the control gate, the lower will be the threshold for the positive voltage applied to the control gate to switch the gate On. This is the erased state.

Vice versa, if a programming voltage applied to the control gate draws electrons from the substrate into the floating gate, this negative charge interposed between the control gate and the channel will require a higher control voltage to switch on the gate. This “synergistic” or “antagonistic” interaction between floating and control gate is common to all forms of flash memory regardless of whether it is NAND or NOR flash.

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Last Updated ( Aug 02, 2010 at 12:50 AM )
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