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| Intel's Sandy Bridge I. Architecture & CPU Performance |
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| Written by Michael Schuette | ||
| Jan 02, 2011 at 12:37 AM | ||
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Page 10 of 23
Out of Order execution is an important part of any modern microprocessor. In short, incoming instructions are decoded as mentioned on the previous page and then either one of two things can happen, namely, the Uops are executed “in order”, that is as they are pipelined or else, they are re-ordered through out of order scheduling. In a very simplified analogy, the Uops are coming in from the front end and, depending on the program order, they are sent to the execution units and later retired. The rationale is to increase instruction level parallelism and, thereby, performance. In Sandy Bridge, Intel is pursuing the same strategy as what AMD is promising with the Bobcat and Bulldozer architecture, that is, Sandy Bridge is moving away from a centralized retirement register file to a physical register file. As a consequence, it is no longer necessary to have a copy of every operand needed associated with every µOp , rather, a single copy of every operand suffices for all µOps. Without this, AVX with its 256 bit operands would not be possible, or at least, carrying the AVX operands along with every µOp would require huge amounts of register real estate and, not to forget, power to move the data.
Putting it All Together There are a number of additional improvements that are mostly incremental, for example the improvements on the execution clusters to accommodate AVX instructions and the memory clusters but they are not as essential for distinguishing Sandy Bridge from its predecessors as the other features we hi-lighted. So, let's just wrap this up by putting the entire processor together:
We'll dig into the on-die graphics in a separate article, for now, let's look at today's candidates.
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| Last Updated ( Jan 17, 2011 at 01:16 PM ) | ||
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