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Intel's Sandy Bridge II: HD Gfx and AVX Print E-mail
Written by Michael Schuette   
Jan 16, 2011 at 06:38 PM

The biggest market segment in the PC industry can be quite simply be described as the one that does not use any discrete graphics and instead relies on an integrated display or graphics processing unit. Whether it is Atom or Ion or any other mainstream platform including laptops, the growing trend has been to consolidate the graphics with the chipset. At the same time, the chipset has more and more become part of the CPU by integrating the memory controllers and even at least some lanes of the PCie interface on the central processor. With the introduction of the Core i5 Lynnfield hybrid designs featuring two different dies on a single CPU package, Intel has taken this kind of integration to the next level by adding a GPU to the CPU, at least to the point where the two units were on the same package .

If Intel's Smithfield to Kentsfield transition was an omen for things to come, it should be no surprise to see that the next step after having a chipset or two different ICs on one package needed to be the full integration of everything into a single die. The integration includes the different I/O interfaces, namely memory controller, PCIe and DMI controllers as well as a fully functional GPU plus streaming video processor with integrated display port to provide TMDS functionality.

Among the issues that any integrated graphics have faced in the past was memory starvation. If the GPU has to rely on the system memory alone, then the access latencies and also bandwidth restrictions are such that regardless of how powerful the actual GPU is, the performance will always be limited. Ways to work around this issue have included the addition of a dedicated “display cache” in the form of typically an SDRAM component of whatever generation prevailed at the time, that is SDRAM, DDR or any of the later generations of the latter. Even the “display cache” did not solve some of the fundamental data requirements, simply because of the incurred latencies and bandwidth problems.

To be true, CPUs face exactly the same problem, that is, if the system memory were the only memory , the overall performance would plain and simply tank, which is the predominant reason for the well established addition of several levels of cache. In the case of multicore CPUs, the caches are segmented, that is, every core has its own private cache levels but also, at least in the case of the latest few generations, a shared cache level is present, which, moreover, doubles as snoop filter.

To close the cycle, if all accomplishments and optimizations of modern CPU architecture are taken into account for the design of a fully integrated Super-CPU/GPU, the addition of the GPU execution units to a single die can by-pass at least some of the restrictions faced by GPUs as part of the chipset, simply by granting the GPU access to the shared processor cache. In the case of Sandy Bridge, this is the last level cache or LLC that takes over as local frame buffer.

Along these lines, it is extremely important to see how the amount of LFB influences the performance of the graphics processor. Keep in mind that every garden variety graphics card nowadays has at least 256 MB of frame buffer, in most cases, even the entry levels don’t start below 512 MB, which, for all practical purposes, leaves enough un-used memory space to avoid the necessity of hitting the main system memory. In the case of the Sandy Bridge solution, we all of a sudden hit a time warp to go back to the levels of the Matrox G200 in its original form, sporting 8 MB of local memory. And that refers to the best case scenario, namely the Core i7 models. Because of the smaller LLC size in the Core i5 and Core i3 models, the memory accessible by the GPU’s execution units will also be reduced to 6 and 3 MB, respectively. Bear this in mind when the same HD Graphics 2000 or 3000 unit performs dramatically different on different CPUs.

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Last Updated ( Feb 21, 2011 at 05:08 AM )
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