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Hewlett Packard PA-8800 RISC
Written by Michael Schuette   
Nov 25, 2001 at 07:21 PM

At last week's MicroProcessor Forum, HP's David J. C. Johnson unveiled the details of HP's latest RISC processor destined to redefine performance in Server-Class processors. Following a relatively simple strategy, the PA-8800 processor combines two PA-8700 cores on a single chip to enable symmetric multiprocessing (SMP) on a single processor. Aside from bumping the core speed up to an initial 1 GHz, enhancements include the addition of combined 35 MB L1+L2 cache. The L1 cache consists of 2 blocks of 750 KByte Instruction and data caches for each core for a total of 3 MB. A huge 32 MB L2 cache is placed off-chip on the same cartridge in the form of four 72 Mbit chips using EMS "1 Transistor SRAM technology". Conservative estimates about the performance of the new PA-8800 processor are in the range of 900/1000 SPEC 2000 int/fp units and 800,000 transactions per minute in server applications.

Last Updated ( Dec 12, 2008 at 03:44 AM )
Strategies for Maximizing the Revenue of Intellectual Property
Written by Michael Schuette   
Nov 11, 2005 at 10:00 AM
Patents are only good if they are used. Use of a patent can entail securing of a market segment, litigation against infriging parties violating the patent protection of a disclosed invention or sharing of the technology with third party manufacturers in exchange for royalties and licensing fees. The latter is by far the most desirable and easiest approach, particularly if the two parties involved share mutual interests and the willingness to cooperate. Often enough the expectations of the licensor are somewhat different from those of the licensor, in that case, a third party mediator can be invaluable.
Last Updated ( Nov 28, 2008 at 03:39 AM )
AMD Athlon64 3800+
Oct 29, 2005 at 05:04 AM

AMD has finally released the Socket 939 version of their Athlon64 processors, which includes the Athlon64 FX53 (Socket 939), the Athlon64 3800+ and the Athlon64 3500+ with the two latter running the dual memory controller but being restricted to the smaller 512 kB L2 cache of the Newcastle die. However, the entire family of Socket 939 processors is capable of running unbuffered memory, which shaves off one bus cycle on each initial memory access.

Aside from the price advantage over the Socket 940 processors, is there any gain in performance caused by the lower latency memory access? Moreover, does the cache reduction hurt the performance and if so, what are the critical applications?

We have looked at the performance of the new platform from a variety of different angles, including different memory configurations that can make quite a difference. After all, AMD processors are more dependent on low latency memory and, by extension, on open pages..

Last Updated ( Jan 08, 2009 at 02:49 AM )
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