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Here is one way out

Without going into too much detail, there are several ways to overcome this problem from the end of the DIMMs. The most widely used employs buffering or registering the individual chips. The register serves as an interface between the individual chips and the chipset in that it can redistribute the address lines necessary to access the individual cells.

But there is also another problem. Each memory chip has a certain capacitance and the memory clock has to come up with enough current to charge each cell. Here is where the register chips can also be of tremendous help since they take over the role of the clock generator. Consequently, all the chipset sees is the limited amount of capacitance inherent to the register chips and that again helps to increase the amount of system memory. In order to synchronize the chips, there is another component necessary, the PLL or phase lock loop. The main problem with this design is that, in order to use the register as an interface and synchronizing unit, the register has to generate its own signals and that causes a performance hit in the form of an additional penalty cycle.

The move to 8 bit parts

Enough reason to look at the first unbuffered 256 MB DIMMs introduced recently by Corsair using double sided 16 chip design based on Toshiba chips in 16M x 8 bit double sided (16 chips) configuration.

Specs at one glance

Corsair PC-100 265 MB DIMM. The BX-2 suffix on the label indicates the CAS-2 part

PCB design

• 6 layer PCB, 168 pin

Organization

• 16 chips, 32M x 4 / chip for a total of 32M x 64 bytes = 256 MBytes

Toshiba 16Mx8 chip used to achieve 256 MByte density

Timing parameters

• Clock access time (tAC): 6 ns
• Clock cycle time (tCK): 8 ns
• CAS delay at 100 MHz: 2

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