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• Use screen capture to save the images of the 256 entry offset matrix at different BIOS settings and import them into Photoshop for pixel subtraction.

The screen capture for the failsafe setting was subtracted from the Ultra2 screencapture of WPCredit. The only areas that are hilighted are the areas showing pixel differences or, by extension, the registers that have changed. It is now possible to look up the hex code of the respective offset settings in the original capture. The same procedure was performed for all settings, from failsafe to ultra2. In the C-revision of the ALiMAGiK1 chipset, each DRAM performance setting changes eight offsets (12 in the B revision)

• Convert the individual hexadecimal numbers into binary code

The individual hexadecimal values for each offset changed from one DRAM Performance setting to another were entered into an Excel Spread Sheet and converted into binary format. Please consider that each offset consists of 8 bits but Excel does not display numbers starting with 0. Therefore, 101 would correctly read 00000101.

• Use the datasheet of the chipset to decode the individual binary bit assignments relating to the respective offset. Despite the simplicity of this approach, with the B- revision of the ALiMAGiK1 chipset, it turned out to be a mammoth task since no less than 12 registers were changed from one DRAM timing setting to the next. Some of the settings were not explained in the datasheet either, others were floating tri-state bits that randomly change upon each reboot, others again were patches for incorrectly functioning registers. Fortunately, with the C revision, things were cleaned up substantially, resulting in only a handful offsets that are changed throughout the different timing settings.

• CAS latency: 2
• Refresh Queue: 8 Depth
• Enhanced Page Mode Timer: 128 Clk
• Refresh Rate: 15.6 µsec
• CPU / Memory Clock: 133 MHz (266 MHz data rate)

Using the ALi M1647 white papers, it was possible to decode the bit assignment into some meaningful timing parameters.

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