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Inside the ALiMAGiK1 BIOS

• R/W Turnaround: the number of wait states after a read until a write command can be issued. Lower numbers result in faster bus-turnaround and, thus, better performance.
• Highway Read: If no operation is scheduled (NOP), the memory command bus is idle-parked, meaning that it goes into standby mode if no consecutive read commands are scheduled. If the idle-park bit is disabled, the memory command bus will be parked on CAS READ, which results in a zero latency on the next read command.
• DDR Read Path Short Latency Mode: This feature applies for DDR only and specifies the time when a read command can be issued (during an ongoing burst).
• tRAS: number of cycles necessary to develop the full charge differential between bit and reference lines to restore the data in the memory cells. Also called the minimum page open time for the reason mentioned.

• tRCD: RAS-To-CAS Delay; bank activate time, the minimum time after a bank activate command until a read command can be issued.
• tRP: RAS Precharge; after a page miss or if a page expires, the RAS lines have to be reset to a neutral state by precharging them before the next bank activate command can be issued.
• tRC: Bank Cycle Time; The sum of tRAS and tRP.
• tDPL: Data Phase Latency; Turnaround between the last Write Data Phase until a precharge command can be issued. Also called tWR or write-to-read interval.
• PLT Enable: The M1647 memory controller offers the possibility to close all pages if the Page Life-Time counter expires
• PLT: Page Life-Time; One of the fundamental differences between the M1647 memory controller and the controller as implemented in the AMD 761 North Bridge is the way of how the page expiration is controlled. The AMD 761 controller has a so-called Page Hit Limit (PH Limit), which limits the number of consecutive page hits and forces a page to be closed before it expires. The ALi M1647 controller does not measure page hits but relies on bus cycles to determine the expiration of a page. However, this timer only becomes active after the bus is idle since each read / write command resets the counter. As a consequence, as long as consecutive R/W commands are issued, the page stays open until a miss occurs.
• MWB Write Buffer Timeout Flush: Master Write Buffer Timeout Flush; the MWB has a buffer valid window that can be preset to a certain number of memory cycles, after which it will be flushed. Disabling the force-flushing can increase performance but also bears the inherent risk of data corruption.

AMD 760 chipset

The board used for compatibility testing was a preproduction sample of the FIC AD11. In the case of the AMD 761 North Bridge and the Award BIOS as written for e.g. the FIC AD11, things are a bit easier since the individual parameters are listed separately in the Advanced Chipset page. As a caveat, the testing was limited to 100 MHz since the board used would not run the 133 MHz bus speed. This issue will be resolved in the final revision of the AMD 760 chipset and the production version of the AD11.

Memory adjustments in the FIC AD11 as representative board featuring the AMD760 chipset.

In this case there is no doubt what the individual settings stand for. Adjustments of the timing parameters allow the following settings:

• SDRAM PH Limit: 1, 4, 8, 16 page hits
• SDRAM Idle Limit: 0, 8, 12, 16, 24, 32, 48 cycles
• tRC Timing: 3, 4, 5, 6, 7, 8, 9 cycles
• tRP Timing: 3, 2, 1, 4 cycles
• tRAS Timing: 2, 3, 4, 5, 6, 7, 8, 9 cycles
• CAS Latency: 2.5, 3 cycles
• tRCD Timing: 1, 2, 3, 4 cycles

The board tested had the glitch that the tRC value did not automatically adjust to the proper setting, that is the sum of tRAS and tRP. We assume that this is merely a glitch in the display, though.

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