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tRAS and tRAS Violation

The explanation in this case is the tRAS value of 4 cycles that kicks in at the Ultra and Ultra2 settings. Four cycles at 133 MHz are equivalent to 30 ns. What is the significance of tRAS? I am borrowing this line from the LC-BIOS guide:

Why is there a minimum bank cycle time and what is tRAS violation?

After the RAS activates a bank, the data are latched onto the sense amplifiers. The way of how that works is that you have two lines, bitlines and bitlines running in parallel where one of them is the signal and the other is the reference. This is not hardwired but works like line interleaving where each line can be the signal and the other one is the reference.

In other words, tRAS is the time necessary to develop the full charge of the bitlines and restore the data in the memory cells before a precharge can occur. A precharge is the command that closes the page or bank, and therefore tRAS is also defined as the minimum page open time. If you add the precharge (tRP) you end up with the total number of clocks required for opening and closing a bank, in other words the bank cycle time or tRC.

To rephrase this, tRAS is the time necessary to warrant data integrity, not only within the memory array but also within the entire system. If incorrect data are written back to the hard disk, drive corruption is the logical consequence, that is, violating tRAS can, among other things, result in corruption of not only some data on the HDD but also cause bad sectors on the drive.

Let's take a look at how the other candidates perform. As it turns out, only the double sided (64 Mbit chips) are able to function at a bank cycle time of 7 cycles (tRC = tRAS + tRP; 4+3 = 7 x 7.5 ns = 52.5 ns and even at the 140 MHz setting: tRC= 49 ns). All other DIMMs, including the single-sided Micron samples failed at this setting. Keep in mind that the bank cycle time is somewhat related to the depth of a memory chip. That is, the smaller the chip, the shorter can the bank cycle time be. Therefore, it is not surprising that the DIMMs with the lowest depth chips outperformed all other DIMMs with regard to tRAS valid. Keep in mind, though, that the Ultra and Ultra2 settings should only be used when running a 100 MHz memory bus.

Pass or Fail at 133 MHz
(all DIMMs running at CAS-2 except for Mushkin 256 MB at CAS-2.5*)

*because of the higher density of the 256 MB Mushkin DIMM, it is not surprising that it wouldn't run reliably at 133 MHz and CAS-2 since the increased load on the DRAM clock causes additional delays.

How Fast Would They Run?

At the Fast setting, both the double-sided Micron and the 128 MB Mushkin DIMM were operating flawlessly at 140 MHz and CAS-2, At 142 MHz, the system showed signs of instability, which, however, could relate to the CPU as well since the neww Iwill board still doesn't have voltage adjustments. Thus, Vre was shown as 1.72 V by the Hardware Monitor (which appears a bit on the low side). The single-sided Micron DIMM worked up to 136 MHz at CAS-2 but even at CAS-2.5 wouldn't go higher. The 256 MB Mushkin DIMM had no problem at all at 133 MHz but showed signs of instablity at 136 MHz.

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