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LOSTCIRCUITS

SHORTCUTS:
Top page
ALi BIOS issues
hacking the M1647
BIOS parameters explained
Micron's DDR DIMMs
a tale of two Mushkins
memory benchmarks
tRAS violation as limit
real world performance and conclusion
 DDR DIMMs, BIOS and Timing Issues   
Dont Do Rambus
(Review by MS, January 1, 2001)


Performance Differences In Real Life Situations

As shown above, most DDR DIMMs are unable to function at 133 MHz and Ultra(2) setting. Sisoft Sandra picks up some performance edge of this setting, but what about real world applications?

We have answered this question already in the review of the first revision of the Iwill KA266-R. In real-life benchmarks, in this case, Expendable, there was no performance increase at the Ultra settings. On the contrary, the Ultra settings showed lower frame rates than the Fast setting. Using the second revision of the board, the situation changes ever so slightly but there are a few caveats:


Whenever tRAS is set too short, the first thing to notice is, when running Expendable, the little guy starts acting up. That is, instead of running the Timedemo, he is running in circles, starts entire sequences all over again and this, of course, changes the outcome of the frame rate counter since the repetitions are running from the cache instead of the main memory. Depending on the number of glitches, it is, therefore, no problem to achieve average frame rates of 140 fps and higher. This can be easily replicated with any SDRAM system by setting the bank cycle time to the shortest value (with the caveat that HDD corruption may occur). If the glitches occur, however, in a sequence that are running at low fps anyway, or if there is simply a problem with writing the checksum back for any sequence just finished as a signal to load the next batch of data, small Microstalls may occur and the performance will take a hit.

Other factors like R / W Turnaround and Data Phase Latency may as well contribute to the abnormal behavior of the Benchmark. Suffice it to say that the benchmark numbers shown are from runs that did not show any overt abnormalities but please keep these things in mind when looking at benchmarks posted elsewhere.

Expendable frame rates at 1200 and 1260 MHz (133 and 140 MHz memory bus, respectively, CAS-2. In the new revision of the ALiMAGiK1 chipset, the Ultra(2) settings average about 0.5% faster than the Fast setting which is not even significant in terms of statistics.

Conclusion

The first batches of DDR chipset are on the market and there is, at present, precious little supply of DDR memory. The situation is, however, steadily improving, with Micron, Hyundai and Samsung ramping up the production of DDR discretes, closely followed by Infineon. Infineon-based DIMMs were not available at the time of testing but some of their chips are specked at CAS 2 / 133 MHz and we have obtained insider information that they are capable of running 150 MHz (300 MHz data rate) at CAS-2 with a bank cycle time of less than 50 ns.

The main goal of this article was not to play one DIMM (or brand) against the other, the simple fact that we used production DIMMs and compared them with hand picked engineering samples would make such goal an absurd task. The real issues here were to elucidate the timing and performance issues evolving with the new field of DDR technology and to provide some guidance of what is possible and what is not. Furthermore when looking for DDR DIMMs, one should be aware of the different configurations possible and the limitations posed by increasing density.

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