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tRCD becomes the limiting factor

After the above explanation of why DDR DIMMs shouldn't have to many problems with the Column Address Strobe and neither gain too much performance with reduced CAS latency, it is necessary to point out another issue, which, in the DDR platform becomes increasingly important: RAS-to-CAS Delay. To backtrack again to SDRAM, we know that the tRCD is of only minor importance for the overall performance but can also be the limiting factor for overclocking.

The latter part has not changed. Also with DDR, tRCD becomes, in most cases, the limiting factor for overclocking. The reason is that this interval specifies the time allowed for activating a row, which includes the following steps:

• decoding of the row address within the chip
• sensing the data out of the memory cell and amplifying the signal

What about system performance?

tRCD is important in all random accesses or page misses as the first critical word out latency is the sum of tRCD and CAS delay or tRAC. In theory, there aren't any more page misses in DDR than in SDRAM, in practice, there is one major difference which is the shortened page hit limit (PH Limit). To give one example, the AMD 751 NorthBridge allows a PH Limit of up to 64 consecutive page hits. The 761, on the other hand, is set by default to 8 and can in some cases be tweaked to 16. This means that, even if the data of the 9th access are within the same page, the page is forced close, resulting in a page miss where tRCD and tRP become important again. In other words, switching from SDRAM to DDR requires a major re-thinking of the latency strategies when it comes to performance. The impact of shortening tRCD vs. CAS latency in a DDR system is shown below

SiSoft Sandra scores obtained on the EPoX 8KHA running at 133 MHz FSB. Shown are the ALU and FPU scores in MB/sec at 2.5:3:3 (CAS:tRCD:tRP) in the bottom columns. Reducing the CAS latency has only a minor impact on the memory benchmark with only the FPU scores increasing at all. On the contrary, changing tRCD from 3 to 2 cycles results in a substantial increase in bandwidth. Note that the CAS latency is reduced only by 1/2 cycle that is, from 2.5 to 2 cycles which gets absorbed during in page accesses by the early read command anyway.

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