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Summary

Six years after the idea was created, DDR-II finally appears to make an entry in the marketplace. At the same time, the graphics version of the new standard, that is GDDR2 has already become obsolete, reasons being high power consumption along with thermal problems that negate the marginal performance increase found over the original DDR design.

In the graphics sector, the next generation of DDR, that is, GDDR3 has almost overnight become a main player, with a simplified design, lower power consumption and final riddance of some historical DRAM protocol baggage. The design improvements of GDDR3 compared to (G)DDR-II are extremely intuitive, which makes us wonder whether a similar transition could happen overnight in the system memory / desktop segment as well.

We have looked at some of the design features, especially with respect to On-Die-Termination and strobing that, in the case of DDR-II seem to be slightly off-topic and compare them with the respective GDDR3 solutions that appear more cost-effective and power-conserving. At this point it is too early to even provide a crystal-ball view of what will happen but we'll let some of the facts speak for themselves.

The second generation of double data rate memory, that is DDR-II, has finally made its first, sparse appearance in the retail channel. Originally, DDR-II was shown on the different roadmaps scheduled for the third quarter of 2002 to enable 400 MHz data rate DRAM. Indeed, looking back, the highest speedgrade officially available in Q4 2001 and Q1 2002 was PC2100 or DDR266. Suffice it to remind our readers that at this point the official standpoint in the DRAM industry was still that there was no ramping of the operating frequency possible unless the form factor was going to be changed from a thin small outline package (TSOP) to a ball grid array (BGA). Arguments in favor of the BGA form factor centered on the lower impedance and shorter trace length of a solder ball compared to a standard “leg” of the TSOP design.

Interestingly enough, outside of the DRAM manufacturers party lines, almost everybody acknowledged already then that the original speed target of the first generation of DDR, that is, DDR266 had been surpassed. In Q2 2001, Samsung, Mosel and Hynix chips were already running some 150 MHz, a few weeks later, Micron’s DDR 266 components were achieving some 190 MHz clockspeed, and yet another few weeks out, Samsung’s “C” die cranked out an unbelievable 235-240 MHz clock rate, equivalent to DDR480. Yet, the official standpoint remained that DDR333 was not going to be possible unless the transition to a BGA interface was done.

In order to appreciate the above, it is necessary to understand how the DRAM specifications are created, based on proposals that are submitted for review by all JEDEC members and are then discussed during JEDEC meetings and finally balloted for approval or rejection. Simple technicalities can often enough throw a monkey wrench into the procedure, a case in point has been the (much later occurring) DDR400 specification that was delayed over and again because the name DDR400 was already reserved for an upcoming DDR-II standard.

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