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DDR-II

Instead of reiterating in gory detail the DDR-II architecture and feature set, we are going to refer to our earlier article that has covered most of the DDR-II architectural idiosyncrasies. In this article, we are providing a short summary in which we are only addressing some issues that are necessary for an understanding of the remainder of this article. For clarity reasons, we will continue to use the term DDR-II regardless of other terminologies circulating like DDR2 or alternative variations.

DDR-II Core Frequency vs. I/O Frequency vs. Data Rate

DDR-II is running the core at ½ of the clock frequency of the I/O logic. The I/O path, in turn, uses a DDR protocol, that is, transactions on the rising as well as on the falling edge of the clock. This translates into a total of four transfers for each core clock cycle. It follows that a total of four bits of data need to be “readied” at each core clock cycle by prefetching them from the array and temporarily holding them on pipelines within the I/O logic.

Core Frequency vs, I/O frequency vs. Data Rate in SDRAM, DDR and DDR-II (GDDR3) reprinted from our earlier article.

The net effect of this strategy can be described from a variety of different points of view. The first and foremost important aspect is that a slow core can be used to achieve high data frequencies. For example, a 100 MHz DRAM core can be used to achieve DDR400, a 133 MHz DRAM core can output data at 533 MHz. Related and second in line is the fact that a lower core speed will result in lower power consumption since power consumption is a linear factor of the operating frequency. Third, because of the lower frequency, it is possible to lower the operating voltage from 2.5V to 1.8V.

The official naming convention for the different voltage interfaces specifies the DDR interface as SSTL-2 (2.5V), whereas DDR-II uses SSTL-18 (with ODT; we will cover the details below)

On the other end of the spectrum is the fact that the higher speed is bought at the expense of granularity of the data access and the most obvious effect is the increased latency of the DDR-II architecture. Whereas current DDR (I) is capable of running at 400 MHz data rate with one penalty cycle each for the Bank Activate (tRCD), the Read (CAS) delay and the Precharge Delay (tRP), that is, at 2:2:2 latency settings, DDR-II will incur three penalty cycles for each of the above mentioned parameters, and run at 4:4:4 at the same operating frequency.

The numbers just mentioned only hold for Read accesses, on Writes, the situation is slightly worse. DDR (I) writes are executed at CL-1, that is, immediately after a write command is given and without any penalty cycles. In DDR-II, the Write CAS Delay is specified as Read latency minus 1, that is, a CL-4 module will run at a write latency of 3 clocks. One of the reasons for the increased Write latencies is that it allows to turn off the recievers on the memory die and, thus conserve power.

next page:    => On-Die Termination: Trade-off Between Power and Frequency =>