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Preamble and Postamble

One thing that is not explicitly clear to the layman is that DRAM is not always running at full load, that is, there are idle periods interleaved with periods of reads and writes. For the data path, it is not necessary to maintain a data strobe at all times, on the contrary, if there are no data on the bus, there is no need for a data strobe either and, consequently, it is turned off in order to save power, as well as to avoid timing conflicts between different ranks on the same “shared” data bus.

Only during periods of data transfers is a strobe signal generated, which, however, differs between Read and Writes with respect to its origin and its data alignment. On Reads, the data strobe is issued by the memory device and sent towards the controller where it is received along with the data as a clock forwarding signal. On Writes, the strobe is generated by the memory controller and sent along with the data to be written and in this case, the DRAM acts as a receiver of the forwarded clock signal.

Trace Inertia

The problem with eliminating data strobes under idle conditions is that electrical signal lines have a tendency to adapt to these periods of idleness, and, as a consequence, build up a certain level of inertia. The result is that the first “pulse” of signal will have to overcome the electrical inertia of the traces and, consequently, have a degraded signal integrity. With every subsequent data transfer, the signal integrity will increase until it reaches steady state of quality at the third or fourth transfer. From a signaling standpoint, the logical solution is to issue a preamble, that is a strobe signal BEFORE the actual data transfer starts and then to throw away this first cycle.

In the case of DDR and DDR-II, the idle state of the Data Strobe or DQS returns is Vref, that is the center point between power and ground. In the case of DDR, this means that Vref is at 1.25-1.3V (depending on the speedgrade and applied memory voltage), in the case of DDR-II, Vref is at the centerpoint of the voltage swing between 0 and 1.8V, that is 0.9V. As soon as a data transfer is started, the DQS is pulled down from Vref to a low state where it waits for the first signal. Since the signal can be either high or low the wait time is specified as one full clock cycle. This mode is called a preamble level. From a performance standpoint, the preamble is negligible since Bank Activate and Read commands take enough time for their execution so warrant pushing a “cleaning signal” down the data path. After the end of the data transfer the strobe returns to its idle level during a postamble.

Current DRAM including single data SDRAM DDR and DDR-II allow two modes of data transfer, the first being sequential, meaning that the data transfer starts at bit 0 and continues in ascending order, the second being called interleaved which means that the data transfer can occur in two pairs of bit, that is either 1,0-3,2 or 3,2-1,0. Sequential mode is supported mostly by older IBM system architecture whereas interleaved mode is the current mode of operation supported by e.g. Intel and AMD.

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