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DDR-II vs. GDDR3
The Forgotten Features |
(Review by MS, June 7, 2004)
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OCZ Low Latency DDR (I)
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DDR3 and Future DRAM Generations
DDR3 standards are currently still in the process of being defined and therefore, it is impossible to predict the exact specifications. However, in the broad spectrum of dedicated graphics memory, GDDR-II, which was a specialized form of DDR-II has already reached end-of-life status in a rather ephemeral presence in the market.
Reasons for the transition beyond DDR-2 were primarily the frequency limitations, partially caused by the lack of termination on address and command lines as well as issues with heat and power. High-end GDDR-2 components used an increased voltage swing, that is from 0 to 2.5V instead of the 1.8 V specified for desktop DDR-II and the result was an increased power drain through the center tap ODT design with the resulting increase in heat dissipation.
Termination to VDDQ instead of Center Tap
This is where one of the main improvements of GDDR3 over previous DDR generations comes in, namely, the termination goes with a single resistor to VDDQ (the output voltage “high” level). This voltage interface specification is called pseudo open drain or POD-18 (since VOH equals 1.8V). The trick in this case is that in idle state, the DQ lines are at a high level anyway and therefore, there is no voltage gradient and, by extension, no current drain. Under load, only at the low state of the output signal (VOL) is there any current drain through the termination pathway whereas at the high voltage levels and in idle mode, no power will be wasted.
The voltage swing is, moreover, reduced to 1.0, that is VOL is no longer at ground but rather at 0.8V to further reduce the current drain at VOL. As a result, VRef is at 1.26, slightly below the center-point between VOH and VOL (1.3V).
The lower power drain on the POD interface allows an unproblematic implementation of termination also for the address and command bus, thus pushing the frequency limitations further out with currently shipping components already at 1200 MHz data rate (point to point on graphics cards).
For an easier implementation of the clock forwarding signals, GDDR3 (and most likely DDR3) will trade in the differential strobe that does not allow any improvements on the signal integrity anyway for a pair of self-calibrating unidirectional strobes dedicated to either Read or Write transfers. Moreover, the termination to VOH level allows moving the strobes at idle to VDDQ, which means that there will be no power drain associated with them and, moreover, the strobes will always be valid and can be fired up with ˝ clock cycle of “warm-up time” or technically speaking “preamble”.
Finally, DDR3 will abandon the sequential output mode and only support the “interleaved” mode (not to be confused with bank interleaving), which allows simplifying the memory controller.
Corsair Low Latency DDR
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In summary, DDR-II is an interesting technology with a number of technical limitations that have to be understood in the context of the time at which the idea was born. Keep in mind that that was the time at which PC100 just started to appear in the market and clock and bus speeds that we have gotten used to by now were still beyond imagination. Technology has moved on, processor speed has increased by a factor of 20 and the realization of DDR-II has been delayed to the point where the built-in obsolescence of any design becomes an issue. DDR-II will have its place in the market but it appears as if there may be new standards on the horizon that, based on reduced cost and better performance, could go mainstream even before the acceptance of DDR-II happens.
Special Thanks to Joe Macri (ATI) and Jon Faue (UMI) for helpful discussions
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